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2011-12-02Add ASUS M4A785T-M mainboard supportDenis 'GNUtoo' Carikli
This mainboard is very similar to the M4A785-M, but it has DDR3 instead of DDR2. That's why most of the code was copied or included from the m4a785-m directory Notable changes between the two mainboards include: * the selection of the last microcode (mc_patch_010000b6.h) which made it pass the CPU init. * the selection of DDR3 which made it pass the ram init This change was tested with the Trisquel 5.0 GNU/Linux distribution which uses the linux-libre version 2.6.38-12-generic The mainboard boots fine, however some special care is required for the onboard sound CODEC, and the onboard video chip: * the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue is the same than the ASUS M4A785-M mainboard: It causes a flood of interupts which prevents booting * The internal video chip currently requires pci=nocrs, else the graphics are frozen as soon as the radeon module loads, and dmesg would print the following(the card only has 256M, and the mainboard was equiped with 2G of RAM): [ 3.674762] [drm] radeon: 3584M of VRAM memory ready [ 3.679863] [drm] radeon: 512M of GTT memory ready. instead of : [ 45.876088] [drm] radeon: 256M of VRAM memory ready [ 45.876089] [drm] radeon: 512M of GTT memory ready. * The screen(both VGA and HDMI) flickers at high resolution * Sometimes the computer freeze while changing the resolution (even the serial console stops responding) The following peripherals were tested: * The ath9k PCI wireless card was tested * The SATA hard disk works fine * the USB keyboard and mouse work fine * htop see 2 cores * serial port works under coreboot and GNU/Linux * power off and reboot works CPU frequency cannot be changed yet, this is addressed in a new commit. More detail are available here: http://www.coreboot.org/ASUS_M4A785T-M dmesg is available here: http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html The mailing list thread on the graphic problem is here: http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/457 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-30remove usbdebug.h include from mainboard/romstage codeSven Schnelle
No romstage is supposed to use usbdebug functions/defines directly, so remove all those includes. The usb code is now called and setup from console code. Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/354 Tested-by: build bot (Jenkins)
2011-10-13mptable: Refactor mptable generation some morePatrick Georgi
The last couple of lines of every mptable function were mostly identical. Refactor into common code, a new function mptable_finalize. Coccinelle script: @@ identifier mc; @@ ( -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); | -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); ) Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/246 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Get rid of fixup_virtual_wirePatrick Georgi
As stated in some code files, fixup_virtual_wire was established to avoid touching 200 invocations of the mptable code. Let Coccinelle do it: @@ type T; identifier v; @@ -void fixup_virtual_wire(T v) -{ ... } @@ expression A; identifier v; @@ -v = smp_write_floating_table(A); +v = smp_write_floating_table(A, 0); @@ expression A; identifier v; @@ -v = smp_write_floating_table(A, 0); -fixup_virtual_wire(v); +v = smp_write_floating_table(A, 1); Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/245 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-25Fix up various dsdt.asl filesAlec Ari
Change-Id: I46eb27847deb3a903ac9af347992a9954e50ff6e Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/166 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-24Remove dead codeAlec Ari
Remove dead code, copy and pasted from tilapia's mainboard.c file into various asus mainboard.c files Change-Id: Ic715ccaad8ac0210401d4a99ecb11e943f6afe58 Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/168 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Update AMD SR5650 and SB700efdesign98
This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-04-20run uart_init() from console_init, just like the other console ↵Stefan Reinauer
initialization functions. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-18* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that valueStefan Reinauer
to unify calls to *_enable_usbdebug() * rename *_enable_usbdebug() to enable_usbdebug() * move enable_usbdebug() to generic romstage console init code and drop it from the individual romstage.c files. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx.Zheng Bao
Since the SB700 has changed to sb7xx_51xx, change legacy name in other mainboard. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-08Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the ↵Scott Duplichan
expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF. The patch makes these changes: 1) Remove the BUID swap list from ht_wrapper.c and put it in each of 15 romstage.c files where it is used (AMD family 10h projects). 2) Add a prototype to amdfam10.h. 3) Modify the swap list and test in real hardware for mahogany_fam10 and kino family 10h and confirm HT3 operation for the SB link. Abuild tested. Signed-off-by: Scott Duplichan <sc...@notabs.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01Use subsystem id from devicetree.cb instead of Kconfig and moveSven Schnelle
all boards to the new config scheme. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Make AMD Fam10h CPU microcode updates optional in Expert modeXavi Drudis Ferran
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16Get mptable OEM/product ID from kconfig variables.Uwe Hermann
We currently use "COREBOOT" unconditionally as the "OEM ID" in our mptable.c files, and hardcode the mainboard name in mptable.c like this: mptable_init(mc, "DK8-HTX ", LAPIC_ADDR); However, the spec says "OEM ID: A string that identifies the manufacturer of the system hardware." (Table 4-2, page 42) so "COREBOOT" doesn't match the spec, we should use the hardware vendor name. Thus, use CONFIG_MAINBOARD_VENDOR which we have already as the "OEM ID" (truncate/fill it to 8 characters as per spec). Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as "product ID", and truncate/fill it to 12 characters as per spec, if needed. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11Following patch makes just one fadt.c file. For SB700.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11After this has been brought up many times before, rename src/arch/i386 toStefan Reinauer
src/arch/x86. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-10Add TINY_BOOTBLOCK support for AMD SB700.Uwe Hermann
Factor out the ROM decode enable functionality into bootblock.c and handle it via the usual TINY_BOOTBLOCK mechanism. Use "select TINY_BOOTBLOCK" in the southbridge, not individual boards. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-09Deduplicate various ACPI .asl files.Uwe Hermann
The files debug.asl, globutil.asl, and statdef.asl are duplicated in many K8/Fam10h boards. However, they're neither board-specific nor K8/Fam10h-specific nor AMD-specific, so move them to src/arch/i386/acpi. debug.asl contains generic chunks for I/O port 0x80 handling, and debug output over serial port (init COM port, send byte, send string, etc). globutil.asl contains utility methods for string comparison, string length and similar stuff. statdef.asl contains generic ACPI bit definitions / status codes from the ACPI spec (not board- or chipset-specific). This patch was mostly generated by: mkdir src/arch/i386/acpi svn add src/arch/i386/acpi svn cp src/mainboard/amd/dbm690t/acpi/debug.asl src/arch/i386/acpi/ svn cp src/mainboard/amd/dbm690t/acpi/globutil.asl src/arch/i386/acpi/ svn cp src/mainboard/amd/dbm690t/acpi/statdef.asl src/arch/i386/acpi/ cd src/mainboard find . -name debug.asl -exec svn rm {} \; find . -name globutil.asl -exec svn rm {} \; find . -name statdef.asl -exec svn rm {} \; Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08Move "select CACHE_AS_RAM" lines from boards into CPU socket.Uwe Hermann
All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM" into the socket directories, and remove it from the individual boards. Do the same for Intel CPUs/sockets where all boards use CAR. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08second round name simplification. drop the <component>_ prefix.stepan
the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the <componentname>_ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08first round name simplification. drop the <component>_ prefix.stepan
the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the <componentname>_ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-07Get rid of some unneeded function prototypes in romstage.c files.Uwe Hermann
Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-07Trivial. Fix typo.Zheng Bao
sh> find -name "acpi_tables.c" | xargs sed -i "s/FDAT/FADT/g" Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-06Drop unused/obsolete CONFIG_COMPRESS from a few board Kconfigs.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-06Add initial support for the ASUS M4A78-EM.Juhana Helovuo
Signed-off-by: Juhana Helovuo <juhe@iki.fi> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22Drop per-board ram_check() calls for now.Uwe Hermann
Every board had a slightly different invokation, very often commented out anyway. We could either decide that this is only to be used by developers during bringup (and thus added manually to romstage.c and removed before the board gets committed). This method seems to be preferred from what I have heard on IRC / mailing list in the past. Or, we add the ram_check() somewhere globally and allow the user to enable it via menuconfig (possibly only if EXPERT is selected). Either way, the current method of spreading the calls all over the place is not really the way to go. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Simplify a few code chunks, fix whitespace and indentation.Uwe Hermann
Also, remove some less useful comments, some dead code / unused functions. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Drop excessive whitespace randomly sprinkled in romstage.c files.Uwe Hermann
Also drop some dead or useless code snippets. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Convert boards to use mptable_write_buses.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20Some more DIMM0 related cleanups and deduplication.Uwe Hermann
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do. - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of romstage.c files and lots of spd_addr.h files. Don't even bother for those spd_addr.h which aren't even actually used, drop them right away. - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1, and 0xa0 with (DIMM0 << 1) where appropriate. - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0, SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC. - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines. - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do. Then, replace 0xa0 (which now becomes 0x50) with DIMM0. - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes. - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20Unify DIMM SPD addressing. For Geode, change thePatrick Georgi
addressing scheme to match the rest of the tree (0x50 instead of 0xa0). abuild tested. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Fix/drop some obsolete comments,Uwe Hermann
- s/Options.lb/devicetree.cb/ - s/Config.lb/devicetree.cb/ - s/cache_as_ram_auto.c/romstage.c/ - h8dmr_fam10/README: Drop obsolete comment, we have mc_patch_01000086.h in the tree now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Eliminate SET_NB_CFG_54 option. There was no board thatPatrick Georgi
deselected it, and very likely there won't ever be any hardware that requires it deselected. Keep the "selected" code path around, leading to no functional change. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17This problem was introduced withTobias Diedrich
http://tracker.coreboot.org/trac/coreboot/changeset/3953 Note that all corresponding DSDTs only ever check TOM2 against 0. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16Move the SET_FIDVID* family of configuration options to Kconfig andPatrick Georgi
make their defaults more obvious. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07DSDT.asl should not report the AMD SB600/SB700 RTC as Intel PIIX4Scott Duplichan
compatible. The extended cmos is accessed differently for AMD and Intel RTCs. Not sure what if any OS cares about this distinction, but non-Intel compatible seems like a safer way to report the AMD RTC. Tested with Win7 on Mahogany_fam10 and kino-780am2-fam10. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-06Remove comments that are obsolete since r6028.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05Move QRANK_DIMM_SUPPORT to Kconfig, removing it from romstage.cPatrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05Various PIRQ/MPTABLE/ACPI Kconfig fixes.Uwe Hermann
- Use HAVE_ACPI_TABLES, HAVE_MP_TABLE, and HAVE_PIRQ_TABLE (instead of GENERATE_*) in the board's Kconfig file, as all other boards do. - Add missing HAVE_ACPI_TABLES/HAVE_MP_TABLE/HAVE_PIRQ_TABLE to boards which have the respective files. The only exception: EPIA-M700 doesn't select ACPI, as it doesn't have dsdt.asl. Added a comment that the user is supposed to run the 'get_dsdt' script and edit Kconfig afterwards. - Fix minor warning/error in src/mainboard/msi/ms9652_fam10/acpi_tables.c, now that the file is actually used. - msi/ms9652_fam10: use #include instead of Include() as we usually do now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-31Remove definitions of ACPI_SSDTX_NUM to 0, that's the default anyway.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-26We need to call smp_write_lintsrc() instead of smp_write_intsrc() forTobias Diedrich
local ints. This is wrong in most coreboot mptables, probably all generated by util/mptable/mptable.c. After fixing this now XP can boot in MPS mode on my M2V. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-25Factor out common mptable code to mptable_init().Uwe Hermann
- Drop sig[], oem[], and productid[] fields in all mptable.c files, no longer needed. The sig[] is always the same ("PCMP"), the oem[] is currently also always the same ("COREBOOT"), and productid is being passed into mptable_init() directly as string now. - LAPIC_ADDR is passed in as parameter, too. While at the moment it's always the same value that is passed in, the LAPIC base address could also be relocated theoretically, so keep it as parameter for now. - Fix a few productid entries, they were (partially) incorrect: - DK8S2 (was "DK8X", copypaste) - 939A785GMH (was "MAHOGANY", copypaste) - X6DHE-G (was "X6DHE", incomplete board name) - H8DME-2 (was "H8DMR", copypaste) - H8QME-2+ (was "H8QME", incomplete board name) - X6DHE-G2 (was "X6DHE", incomplete board name) - X6DHR-iG2 (was "X6DHR-iG", incomplete board name) - GA-M57SLI-S4 (was "M57SLI", incomplete board name) - KINO-780AM2 (was "KINO", incomplete board name) - DL145 G1 (was "DL145G1", small fix as per vendor website) - DL145 G3 (was "TREX", wrong board name) - DL165 G6 (was "HP DL165 G6", drop vendor) - S2912 (was "S2895", copypaste) - VT8454c (was "VIA VT8454C", drop vendor, lower-case "c") - EPIA-N (was "P4DPE", copypaste) - pc2500e (was "PC2500", incorrect name) - S1850 (was "S2850", copy-paste) - MS-7135 (was "MS7135") - MS-9282 (was "MS9282") - MS-9185 (was "MS9185") - MS-9652 (was "K9ND MS-9652") - Ultra 40 (was "ultra40") - E326 (was "E325", copypaste) - M4A785-M (was "TILAPIA", copypaste) - P2B-D (was "ASUS P2B-D", drop vendor) - P2B-DS (was "ASUS P2B-DS", drop vendor) - Adapt the mptable utility to use mptable_init() too. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-24Running a checked build of Windows is needed for understanding its various ↵Scott Duplichan
BIOS related BSODs. Win7 checked build complains when running coreboot+seabios: FADT revision inconsistent with length. Revision: 0x1 Length: 0xf4 Expected Length: 0x74 Change the FADT revision from 1 to 3 to match its length and prevent the Windows checked build assert. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.Uwe Hermann
As both ioapic.h and acpi.h define a macro named "NMI", rename one of them (NMI -> NMIType in acpi.h). Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-07Remove duplicate line from pci_ids.h.Jonathan Kollasch
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Jonathan Kollasch <jakllsch@kollasch.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-05- move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1Patrick Georgi
- move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges - drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-05Remove lib/ramtest.c-include from all CAR boards.Patrick Georgi
Remove many more .c-includes from i945 based boards. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-02Allow selecting the physical USB Debug Port on AMD SB700.Uwe Hermann
The AMD SB700 allows changing the physical USB port to be used as USB Debug Port, implement support for this. Also, fix incorrect PCI device of the SB700 EHCI device. Actually, the SB700 has _two_ EHCI devices (D18:F2 and D19:F2), but for now we only use D18:F2. Our generic USBDEBUG code cannot handle multiple EHCI PCI devices currently, AFAICS. Hook up all SB700 boards to the CONFIG_USBDEBUG_DEFAULT_PORT facility. Untested, but should work. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig,Patrick Georgi
rename it slightly, make it visible only on relevant northbridges, drop it entirely from via boards (as they seem to have picked it up from AMD code without using it themselves), and make it default to false for all boards. Some romstages used to set this to "true" (ie. "print debug output"), but I didn't follow up on it in Kconfig - if you need it to debug CAR, enable it yourself. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-28Remove redundant HW_MEM_HOLE_SIZEK and HW_MEM_HOLE_SIZE_AUTO_INC settings.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-25Drop some useless "../../../" in #includes (trivial).Uwe Hermann
Build-tested using abuild. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-24Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure.Uwe Hermann
Without a (currently) dummy set_debug_port() function the build fails, this may or may not be fixed differently in the future. Manually build-tested on all SB600/SB700 boards, and tested on hardware on one SB600 board I own, works fine. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13Add support for Asus M4A785-M.Juhana Helovuo
Signed-off-by: Juhana Helovuo <juhe@iki.fi> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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