summaryrefslogtreecommitdiff
path: root/src/mainboard/asus/kgpe-d16
AgeCommit message (Collapse)Author
2018-11-23mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS
Field 'OEMID' & "OEM Table ID" are related to DSDT table not to mainboard. So use macro to set them respectvely to "COREv4" and "COREBOOT". Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2018-11-21ACPI: Fix DSDT's revision fieldElyes HAOUAS
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version. This will cause the AML interpreter to use 32-bit integers and math if the version is 1, and 64-bit if the version is >=2. Current spec version is 2 for ACPI 6.2-a. Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29626 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Remove unneeded include <lib.h>Elyes HAOUAS
Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-05mainboard: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: Ib3aafcc586b1631a75f214cfd19706108ad8ca93 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29285 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-31reset: Finalize move to new APINico Huber
Move soft_reset() to `southbridge/amd/common/` it's only used for amdfam10 now. Drop hard_reset() for good. Change-Id: Ifdc5791160653c5578007f6c1b96015efe2b3e1e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-22amdfam10: Convert to `board_reset()`Nico Huber
And here comes the mess... This just renames do_hard_reset() to do_board_reset() and keeps current behaviour. As these are never called from chipset or board code but only from common code, it's likely that their implementations are untested and not what we actually want. Also note, that sometimes implementations for rom- and ramstage differ considerably. Change-Id: Icdf55ed1a0e0294933f61749a37da2ced01da61c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29058 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18mb: Fix non-local header treated as localElyes HAOUAS
Change-Id: Ib39305effdb00e032ca07e6d0e0d84cdf3dcf916 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-18cpu/amd: Use common AMD's MSRElyes HAOUAS
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-09-25mb: Use 'unsigned int' to bare use of 'unsigned'Elyes HAOUAS
Change-Id: I3a8e077656df02912b4e67c3947bd5af054a18bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-16mb/*/*/cmos.default: Harmonise CMOS files syntaxElyes HAOUAS
These files are being updated to match the prevailing style of cmos.default files. Change-Id: I47d31d6fec8c9eb856aed0c63824d9556b7705e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15mb/*/*/cmos.default: Decrease debug_level to 'Debug'Elyes HAOUAS
Used default console log level is 7 in src/console/Kconfig. So let cmos.default use the same level as default. Change-Id: Ia39ee457a8985142f6e7a674532995b11cb52198 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-13src: Get rid of non-local header treated as localElyes HAOUAS
Change-Id: I2c5edadfd035c9af08af9ee326a5a2dc8b840faa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-09src/mainboard: Fix typoElyes HAOUAS
Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-25drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese
Logic: If vboot is not used and the tpm is not initialized in the romstage makes use of the ramstage driver to initialize the TPM globally without having setup calls in lower SoC level implementations. * Add TPM driver in ramstage chip init which calls the tpm_setup function. * Purge all occurrences of TPM init code and headers. * Only compile TIS drivers into ramstage except for vboot usage. * Remove Google Urara/Rotor TPM support because of missing i2c driver in ramstage. Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24905 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-09src/mb: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Iedc2e48349e40e94863c8080d11e11dbe6084c9d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04amdfam10: Drop tests for LATE_CBMEM_INITKyösti Mälkki
Change-Id: Ibe16242d98531ff8e8a696f571496c6f46ea964b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-04mb/asus: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Id572144827b515e9e84c51aa3e4f8a20baf1c212 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04sb/amd/sr5650: Fix invalid function declarationsKyösti Mälkki
Change-Id: I5034debc2296352e698898c20910a2d76071e30a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09mb/asus: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8fe817bb514c69a647c2208a0573a2c5fe98722d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-11-23src/mainboard: Fix various typosJonathan Neuschäfer
These typos were found through manual review and grep. Change-Id: Ia5a9acae4fbe2627017743106d9326a14c99a225 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-31AMD boards: Fix function name (soft_reset) in messageJonathan Neuschäfer
Change-Id: Ia21a3e93712bd6b6780fe7308c6cf79c553f4e1b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-10-04mb/asus/kcma-d8,kgde-d16: Don't select SPI_FLASH_WINBONDArthur Heymans
The default for SPI_FLASH_INCLUDE_ALL_DRIVERS is y which already includes this. Change-Id: Ib2de0f384a547240528b18f07327566354164699 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-23mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-06asus/kgpe-d16: Add romstage_handoffKyösti Mälkki
Fix regression caused by commit 9e94dbf ACPI: Get S3 resume state from romstage_handoff Boards with EARLY_CBMEM_INIT are required to provide romstage_handoff structure to signal S3 resume path. Change-Id: I7c9065ccc48dfbdefade698ed275756f17dff7a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06asus/kcma-d8 kgpe/d16: Fix regression for shutdownKyösti Mälkki
Fix regression caused by commit: 714709f AMD fam10 ACPI: Use common fixed sleepstates.asl Adding common sleepstates.asl got lost in rebase process. Change-Id: I4f22ee950ae5637113db8e79ca238cb1b81002aa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Iru Cai <mytbk920423@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-23AMD fam10 ACPI: Use common fixed sleepstates.aslKyösti Mälkki
SSFG was meant to be used as a mask to enable sleepstates _S1 thru _S4. However as a logical instead of bitwise 'and' operation was used, all the states were enabled if only one was marked available. Note that all boards incorrectly had SSFG == 0x0D that previously enabled ACPI S3 sleep state even when it was not available. Change-Id: Ia948becff079383cbf861468da9e8a3ebbf213cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-22AMD K8 fam10-15: Consolidate post_cache_as_ram callKyösti Mälkki
Change-Id: I5e7890aafbc8c80716ee49690e306482a482a863 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20573 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-07-06mainboard/[a-e]: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: Icca8bac5e67f83dfc5a8f5ef1cb87c6432e0a236 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-08device/Kconfig: Introduce MAINBOARD_FORCE_NATIVE_VGA_INITNico Huber
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to use the latter in a choice. Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-06asus/kgpe-d16: Add video card ID for VGA BIOS namePaul Menzel
The comma-separated PCI vendor and device ID is used to associate the VGA BIOS to the video device by using it as the file name of the VGA Option ROM. Change-Id: I755554eeb9a560d034d6e8fe49de619d800ea045 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-06mb/*/*/cmos.layout: Make multibyte options byte alignedArthur Heymans
Changes the offsets of some options so that options that span multiple bytes are byte aligned. To make the cmos.layout file more consistent some things where moved around in the cmos.layout of thinkpads X200 and T400. Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-19mb/asus/kgpe-d16: Enable TPM when selected in KconfigTimothy Pearson
Issue TPM startup on romstage completion via common LPC TPM code if the TPM was enabled in Kconfig. Change-Id: Id886d6aeefa045fb979f128b1cf4c10fff243b24 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19338 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-17mainboard/asus/kgpe-d16: Remove obsolete reference to TPM ASL fileTimothy Pearson
TPM ACPI entries are automatically generated, and the old static TPM ASL file is obsolete. Remove the reference to this obsolete static ASL file. Change-Id: I3cb2a8a3ac337d1de8a3c394d7a28155597239d0 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19283 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-01-24arch/x86: do not define type of SPIN_LOCK_UNLOCKEDPatrick Georgi
This fixes building coreboot with -std=gnu11 on gcc 4.9.x Also needs fix ups for asus/kcma-d8 and asus/kgpe-d16 due to the missing type. Change-Id: I920d492a1422433d7d4b4659b27f5a22914bc438 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18220 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-04amdfam10: Perform major include ".c" cleanupDamien Zammit
Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/17625 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2016-12-26amd-based mainboards: Fix whitespace in _PTS commentsMarshall Dawson
Correct tabs that were intended as spaces. Change-Id: Idcf33d829f87a866b5ed880527102918d5b93842 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17905 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-12-06cpu/amd/mtrr.h: Drop excessive includesKyösti Mälkki
Change-Id: Id404bdab1f2361f1e7d20f7ee72111971863dddf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17736 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06cpu/x86/msr.h: Drop excessive includesKyösti Mälkki
Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already setKyösti Mälkki
It gets selected from CPU_AMD_MODEL10XXX. Change-Id: Iffab43edc1152b07ba2af6273d4b5eb94afe33ba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17692 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-19mb/asus/kcma-d8,kgpe-d16: use MAINBOARD_DO_NATIVE_VGA_INITArthur Heymans
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG should only occur together with MAINBOARD_HAS_NATIVE_VGA_INIT. It seems to be used to just have to have the option to be able to select SEABIOS_VGA_COREBOOT. This patch makes these boards use MAINBOARD_DO_NATIVE_VGA_INIT and MAINBOARD_HAS_NATIVE_VGA_INIT to have it select SEABIOS_VGA_COREBOOT by default when SeaBIOS is chosen. Change-Id: If0a36af1883a3d62b16a61483733be981a85e5e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16981 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-02Kconfig: Update default hex values to start with 0xMartin Roth
Kconfig hex values don't need to be in quotes, and should start with '0x'. If the default value isn't set this way, Kconfig will add the 0x to the start, and the entry can be added unnecessarily to the defconfig since it's "different" than what was set by the default. A check for this has been added to the Kconfig lint tool. Change-Id: I86f37340682771700011b6285e4b4af41b7e9968 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16834 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-26mainboard/*/*/dsdt.asl: Use tabs for indentsElyes HAOUAS
Change-Id: Idef587d8261784e916e8d50f4336cbcfca39b9b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16730 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/a-trend - emulation: Add space around operatorsElyes HAOUAS
Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16616 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-08-22mb/asus/kgpe-d16: Add TPM supportTimothy Pearson
The ASUS KGPE-D16 accepts an optional Infineon LPC TPM module. Expose the TPM LPC device to the host operating system. Change-Id: If500e9162bf1e233ccaa35db79452daa59a34f2f Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/16269 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-21mb/asus/[kgpe-d16|kcma-d8]: Fix whitespace errors in devicetree.cbTimothy Pearson
Change-Id: I49925040d951dffb9c11425334674d8d498821f0 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/16268 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-08-17mainboard: Clean up boot_option/reboot_bits in cmos.layoutNico Huber
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-14src/mainboard: Capitalize ROM, RAM, CPU and APICElyes HAOUAS
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-01Add newlines at the end of all coreboot filesMartin Roth
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15974 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31mainboard: Format irq_tables.cPaul Menzel
Run the command below to format the files `irq_tables.c` of (mostly AMD) mainboards correctly with GNU indent 2.2.10. ``` $ git grep -l 'if (sum != pirq->checksum) {' | xargs indent -l ``` Fix up the following two checkpatch.pl errors manually. ``` ERROR: that open brace { should be on the previous line #1219: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:129: + uint8_t reg[8] = + { 0x41, 0x42, 0x43, 0x44, 0x60, 0x61, 0x62, 0x63 }; ERROR: that open brace { should be on the previous line #1221: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:131: + uint8_t irq[8] = + { 0x0A, 0X0B, 0X0, 0X0a, 0X0B, 0X05, 0X0, 0X07 }; ``` This is needed, so that follow-up commits, fixing checkpatch.pl errors and warnings, won’t run into conflicts with the git commit hooks, when for example, spaces instead of tabs are used for indentation. Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/15932 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-21timestamp: Drop duplicate TS_END_ROMSTAGE entriesKyösti Mälkki
This entry gets added in run_ramstage(). Change-Id: I18cda4ead3614c6d07c3269cbee53e6def6408c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15755 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-31mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port headerTimothy Pearson
The ASUS KGPE-D16/KCMA-D8 have an on-board header for a second RS-232 serial port, however it is disabled by default due to the SuperIO default pin mux settings. Enable the secondary serial port early in romstage to allow use during / after initial boot. Change-Id: I5b83659dd8b0d6af559c9ceccee55c4cc2f17165 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14892 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-05-09mainboard/asus/[kgpe-di6|kcma-d8]: Fix board ROM informationTimothy Pearson
The board information file incorrectly listed an LPC ROM. Fix the information file to show the correct SPI ROM. This patch changes a human-readable file only, and does not alter functionality. Change-Id: Ib5c1789fa636354f2b6c92faf44b45b32d1ec544 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14742 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-26mainboard/kgpe-d16|kcma-d8: Update memory test to include second PRNG stageTimothy Pearson
The existing memory test routine was insufficient to detect certain types of bus instability related to multiple incompatible RDIMMs on one channel. Add a PRNG second stage test to the memory test routine. This second stage test reliably detects faults in memory setup for RDIMM configurations that also fail under the proprietary BIOS. Change-Id: I44721447ce4c2b728d4a8f328ad1a3eb8f324d3d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14502 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14mb/asus/kgpe-d16|kcma-d8: Do not assign IRQ to LPC HW monitorTimothy Pearson
On specific revisions of the ASUS KGPE-D16 (> 1.03G) there is a high (< 1:10) chance of lockup from spurious HW monitor IRQs during LPC configuration. This was originally erroneously identified as a bug within the SP5100 southbridge due to serial console buffering moving the hang slightly before HW monitor setup. It is currently unknown how changing the CBFS layout / code size was able to alter the frequency of the lockup occuring; this odd characteristic made debugging extremely difficult, and it also indicates testing across multiple PCB revisions will be neded to verify that the bug has been completely resolved. It is highly likely that the KCMA-D8 is also affected. As there does not seem to be a reason to keep the HW monitor IRQ enabled, simply disable it on both mainboards. This configuration has passed burn-on power cycle testing with no lockups noted. All other tests noted a lockup in under 25 power cycles or so, with failure typically occuring in under 5 power cycles; the affected Rev. 1.04 KGPE-D16 has cycled 25 times times using this patch with only one failure finally noted. This final failure may have in fact been related to SP5100 Erratum 18 as the frequency is more in line with the errata document guidelines. Change-Id: Ie9f4f37d2c7dfad0a02daff8b75cd2a1e6f1b09a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14333 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08mb/asus/kgpe-d16|kcma-d8: Enable early MCE reportingTimothy Pearson
Change-Id: I55e68c1dba2b5f1d086179af9b3bc30c5e471f6c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14266 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-05mb/asus/kgpe-d16|kcma-d8: Add ehci_async_data_cache CMOS optionTimothy Pearson
Change-Id: I76a1047742369416b90e5c8bf307f85c02ae9bbb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14242 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-05mainboard/asus/kgpe-d16: Add CPB control CMOS optionTimothy Pearson
Change-Id: I28ad2298ad4dfb428dcd41a4f00db88c5e817cd7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13173 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-02-05mainboard/asus/kgpe-d16: Update power LED handlingTimothy Pearson
- Stop blinking when coming out of standby. - Remove code to set blink when going into S3. This never worked correctly. Change-Id: I958990f3203d3cbe7ae64833800d631c1034327f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13171 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01mainboard/asus/kgpe-d16: Wait for all APs to stop before MCT setupTimothy Pearson
Under certain conditions when the APs are still executing during MCT setup the system can hang. This was the root cause of most of the S3 resume failures on this platform; waiting for AP stop before MCT setup allows for reliable S3 resume. Change-Id: I329eea9a8912d7b57efe6aae327d24fd6c3fd782 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13169 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01mainboard/asus/kgpe-d16: Use W83667HG-A specific PS/2 ASL fileTimothy Pearson
Change-Id: I5a4e223b2e247decd30d8fb2a083be4cff6500a4 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13166 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01mainboard/asus/kgpe-d16: Update DSDT with new devices and bump versionTimothy Pearson
Change-Id: I15fedb067f1911799f7528b60b8754f2984b38ec Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13161 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-02-01mainboard/asus/kgpe-d16: Add support for lifted BSP APIC IDsTimothy Pearson
Change-Id: Ic4b68a032068208d56b2a04150f7fc7d61b38eba Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13164 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01mainboard/asus/kgpe-d16: Add missing IRQ route to mptableTimothy Pearson
The IOMMU/HT device was not routed correctly; add the proper APIC mappting to the mptable generation code. Also clarify comments surrounding the pin mappings. Change-Id: I72ceb0f22dabdfa71a1f6231ccb841face08ff7a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13163 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01mainboard/asus/kgpe-d16: Clean up legacy PIRQ table codeTimothy Pearson
Change-Id: Ib4f46944f076f1e696cf16a1e532eb8635b603c9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13162 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01mainboard/asus/kgpe-d16: Use W83667HG-A SuperIO instead of NCT5572DTimothy Pearson
Change-Id: If67999098fbe2831eeb30cb8b362c558db5d2688 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13157 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-01-29mainboard/asus/kgpe-d16: Use stock PS/2 ACPI ASL fileTimothy Pearson
Change-Id: Iad724e9e1d3e64e2af3f74fed9dec30aa34e2af5 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13153 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-29mainboard/asus/kgpe-d16: Enable ASUS MIO audio optionTimothy Pearson
The KGPE-D16 supports an optional MIO audio card, which connects to the on-board HDA interface of the SP5100. Enable the HDA interface for use with the MIO card. Change-Id: Idfe069f4bce7b94a7460bc7fcdd378eb57e51fda Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13152 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-29mainboard/asus/kgpe-d16: Move memory test before IMD setupTimothy Pearson
Change-Id: Ic6fbf6688e4c2adc85e4eb9fa17e79d29dda58c0 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13151 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22lib: compile mdelay for romstagePatrick Georgi
Mimicking change I7037308d2, always compile mdelay for romstage. The boards that #included delay.c in the romstage now rely on the linker instead, which is a desirable cleanup. Change-Id: I7e5169ec94e5417536e967194e8eab67381e7c98 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13115 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07mainboard/asus/kgpe-d16: Enable romstage microcode spinlocksTimothy Pearson
Change-Id: I93687efc5405359286d3197f0e59ec3b118c5100 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12809 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-18mainboard/asus/kgpe-d16: Enable CBFS spinlocksTimothy Pearson
Change-Id: I8f6226d3e74ac5c7f29f708128a7502ced1287bf Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12062 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-15mainboard/asus/kgpe-d16: Enable romstage spinlocksTimothy Pearson
Change-Id: Iac1adbeacdcded7faff2443b78a491cbb8a90fe8 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12628 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-10ACPI: Work around IASL warning reading/writing same registerMartin Roth
The newer versions of IASL are unhappy when an operator has the same object as both source and destination. The warning can be completely disabled with a command line argument, but in general, I'd really rather not just disable warnings. The bits in this register are write 1 to clear, so reading and writing the same register is what we want to do. Instead, store it in a temporary register then write it in a second operation. Fixes warning: dsdt.aml 1396: Store(PWST, PWST) Warning 3023 - ^ Duplicate value in list (Source is the same as Target) Change-Id: I52d73d4431db237be83016d67cd397f31b53d9c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-07mainboard/asus/kgpe-d16: Use I/O PCI access in bootblockTimothy Pearson
The existing code incorrectly used standard PCI access calls in the bootblock. Use the I/O PCI access calls as the normal PCI access mechanisms have not yet been set up. Also ensure the recovery jumper GPIO has been set to input mode before reading it. Change-Id: Id626d01526427004b2404e4d9b44d7c987d172d1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12651 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-12-01mainboard/asus/kgpe-d16: Enable GART by defaultTimothy Pearson
Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12067 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-30mainboard/asus/kgpe-d16: Limit HT speed to 2.6GHzTimothy Pearson
The CPU <--> CPU HT wiring on this board has only been validated to 2.6GHz. While higher frequencies appear to function initially, and in fact function when only one CPU package is installed, dual CPU package systems will lock up after around 6 - 12 hours of uptime due to presumed HT link errors at the higher (>= 2.8GHz) HT clocks. If applications are not being used that stress the coherent fabric, then the uptime before hang may be much longer. Users attempting to overclock the HT links are advised to "burn in test" the HT links by running memtester locked to a node with no local memory installed. Change-Id: I8fae90c67aa0e8b103e9b8906dea50d1e92ea5a9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12064 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-26mainboard/asus/kgpe-d16: Add missing IOMMU setupTimothy Pearson
Change-Id: I9a00bdbcd47804b6d83c0231cd515773d02ff951 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12527 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-26mainboard/asus/kgpe-d16: Add IOMMU nvram configuration optionTimothy Pearson
Change-Id: I45b04e8fbdfc65603e1057f7b0e5a13d073fe348 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12048 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24amd/amdfam10: Control Fam15h cache partitioning via nvramTimothy Pearson
Add options to control cache partitioning and overall memory performance via nvram. Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24northbridge/amd/amdfam10: Rename mislabeled iommu nvram option to gartTimothy Pearson
Change-Id: Ia24102e164eb5753ade3f9b5ab21eba2fa60836b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12046 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-23southbridge/amd/sr5650: Add IOMMU supportTimothy Pearson
Change-Id: I2083d0c5653515c27d4626c62a6499b850f7547b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12044 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-21mainboard/asus/kgpe-d16: Update NB VDD upper voltage limitTimothy Pearson
Certain older Opteron processors use a higher (+1.2V) northbridge voltage. The existing code assumed the use of +1.1V northbridge voltages and threw an alert when the older Opterons were installed. Update the permissible NB voltage range to include both the 1.1V and 1.2V Opteron processors. Change-Id: I35c90f37d180f59c53d0d2bf3ff0eaf985b26da3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12507 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequenciesTimothy Pearson
Change-Id: Ifa1592d26ba7deb034046fd3f2a15149117d9a76 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12027 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-19mainboard/asus/kgpe-d16: Fix I/O link detectionTimothy Pearson
Change-Id: Ibefc9dc2e1e0267389eb8d716408bae6026ce084 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12024 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-18cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequenceTimothy Pearson
This fixes Family 15h multiple package support; the previous code hung in CAR setup and romstage when more than one CPU package was installed for a variety of loosely related reasons. TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors and several different RDIMM configurations. Change-Id: I171197c90f72d3496a385465937b7666cbf7e308 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12020 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-12mainboard/asus/kgpe-d16: Add sata_alpm CMOS optionTimothy Pearson
Change-Id: I2f2658eb8b3142c86fef4ee50792f51954686cca Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12409 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12mainboard/asus/kgpe-d16: Add dimm_spd_checksum CMOS optionTimothy Pearson
Change-Id: I12323d76ab90f643f4dd4351d7e99824ec24f9be Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12408 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-12mainboard/asus/kgpe-d16: Add missing IRQ routing for PIKE cardTimothy Pearson
Change-Id: I6eba36dad71a2a2713181382484dc0e0976e1dad Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11988 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11mainboard/asus/kgpe-d16: Add maximum_p_state_limit CMOS optionTimothy Pearson
Change-Id: I9a7049fd5601da10a954e02427ad59189fa93fa9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12407 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-11-11mainboard/asus/kgpe-d16: Set SP5100 subtypeTimothy Pearson
Change-Id: If839fd71ed12c1fe27aeab374e242a6855737f5d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11994 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11mainboard/asus/kgpe-d16: Add SATA AHCI mode CMOS optionTimothy Pearson
Change-Id: If7b6062fd4df16ae2864b5d9adfdd19c4356691c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12400 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-11-11cpu/amd: Add CC6 supportTimothy Pearson
This patch adds CC6 power save support to the AMD Family 15h support code. As CC6 is a complex power saving state that relies heavily on CPU, northbridge, and southbridge cooperation, this patch alters significant amounts of code throughout the tree simultaneously. Allowing the CPU to enter CC6 allows the second level of turbo boost to be reached, and also provides significant power savings when the system is idle due to the complete core shutdown. Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11979 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-11mainboard/asus/kgpe-d16: Enable CC6Timothy Pearson
Change-Id: Iae1cbe7d3a6471561abfdb8e182bc764c38bb222 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11978 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-11-11amd/amdmct/mct_ddr3: Use training values from previous boot if possibleTimothy Pearson
DRAM training accounts for most of the romstage startup time, yet if the hardware configuration has not changed from the previous boot the previously discovered training values are still valid. Use them if the DIMM configuration has not changed since the last boot. The SPD values of all installed DIMMs are hashed and stored in the S3 resume data area of the main system Flash device. If a DIMM is changed the hash will almost certainly change as well, forcing retraining on next boot. Change-Id: I37ed277b16476d38e4af76c6ae827a575c6b017d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11976 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-11mainboard/asus/kgpe-d16: Set correct supported SATA port countTimothy Pearson
Change-Id: Ia5c00f07de81d409e6215cc0944d64d00e47b795 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12401 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 19:59:44 +0000