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We deal with mb/lippert/frontrunner-af later since it currently
does not include <cimx/sb800/acpi/fch.asl>.
Change-Id: I30b611fc1fb01777223d7222adc96308a247a35c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50591
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Not referenced anywhere in ASL.
Change-Id: I52ac4722e48e1cc377386316dc034fb45a98181a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50471
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50539
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use global variables to provide mainboard USB settings, and have the
northbridge code copy it into the `pei_data` struct. For now.
To minimize diffstat noise, this patch does not reindent the now-global
mainboard USB configuration arrays. This is cleaned up in a follow-up.
Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50538
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Desktop boards do not have any backlight control.
Change-Id: Ie9f5f4d7e6ae09b3d664d53e4c03157fd4ed088e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The southbridge ASL already includes this file.
Change-Id: I492d4c860a50ac98acbcb3a51fa4d47c94baade3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Variable PICM was not inside GNVS region and can use a static
initialisation value.
For most AMD platforms PICM default changes from 1 to 0.
Fix comments about PICM==0 used to indicate use of i8259 PIC for
interrupt delivery.
Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initialize variable to 1 to indicate AC power supply.
If platform has EC it will set this correctly based on
whether plugged on the charger or not.
Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generated 'build/dsdt.dsl' are identical.
Change-Id: Ief7ea77f8081cd6b7fb18fbf1d25c7394daca07d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46154
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generated 'build/dsdt.dsl' are identical.
Change-Id: I100b6c596d8a1dd74f096f71675026618da32e6f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Objects that are created with acpigen need to be declared
with External () for the generation of dsdt.asl to pass
iasl without errors.
There are some objects that are common to all platforms,
and some that should be declared only conditionally.
Having a top-level ASL helps to achieve this.
Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Use the same variable name as soc/intel to implement a common
_PIC method at top-level ASL.
Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Functionality depends of CMAP and CMBP references inside board
specific ASL implementation. Only roda/rk9 and roda/rk886ex has
that.
Change-Id: I4da8292375cb589d67dc68496b1e81971bc2a61f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49274
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Having some symmetry with <soc/nvs.h> now allows to reduce
the amount of gluelogic to determine the size and cbmc field
of struct global_nvs.
Since GNVS creation is now controlled by ACPI_SOC_NVS,
drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne
cannot have this selected until <soc/nvs.h> exists.
Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
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There's no need to have them in the devicetree. ACPI generation can now
be simplified even further, and is done in subsequent commits.
Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46908
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename acpi_create_gnvs() functions under mb/ to reflect
their changed functionality.
Remove now empty mb/acpi_tables.c files.
Change-Id: Ia366867ef73d1ade9805dc29b8e14b3073f44f60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48707
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop VR configuration since it matches the platform defaults.
Change-Id: I92007f4ff9d093c9573bb1ee13e64eb2f38af4f4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: Ic39b4c70ccb9ec21780c937322d63820064abbd1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49185
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop DEVICETREE from Kconfig since it matches the default value.
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: Idbcd49cca6494ae2da0f364c24638d7ca11911da
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The MAINBOARD_POWER_ON_AFTER_POWER_FAIL symbol was removed in
Commit 9faae2b939.
The default is currently to keep power off after a power failure.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ib2ef450f5c64f663b9aa88f8870250e92898e308
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47671
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure MAX_CPUS in SoC Kconfig with 8 as default value and remove it
from every mainboard where 8 is used.
Change-Id: I825625bf842e8cd22dada9a508a7176e5cc2ea57
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49105
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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They aren't specific to AC power operation anymore. Also adapt autoport.
Change-Id: Ib04d0a08674b7d2773d440d39bd6dfbd4359e0fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49089
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All mainboards use the same values for AC and battery, even desktop
boards without a battery. Use the AC values everywhere and drop the
battery values. Subsequent commits will rename the AC power options
accordingly, and will also clean up the corresponding acpigen code.
This is intentional so as to ease reviewing the devicetree changes.
Also update util/autoport accordingly.
Change-Id: I581dc9b733d1f3006a4dc81d8a2fec255d2a0a0f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Only Sandy Bridge MRC stores scrambler seeds in CMOS. Non-Sandybridge
boards ended up with these entries because of copy-paste programming.
Change-Id: I5a5bda6ea4e63ba03a4219bb2a6aa546bb6ecd7a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47149
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Time has shown that using spaces never converges into proper alignment.
Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Most of these comments have been copy-pasted or serve no purpose other
than to eventually turn into misleading info. While the description of
the first 120 bits of CMOS could be useful, it should instead be added
to the documentation for the CMOS option infrastructure, or /dev/null.
Moreover, trim down newlines to no more than two consecutive newlines.
Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and
set the FSP option for PM ACPI timer enablement from its value instead
of using the old devicetree option.
Also drop the obsolete devicetree option from soc code and from the
mainboards and add a corresponding Kconfig entry instead.
Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, Google Wolf remains identical.
Change-Id: I710581156937b042ba4cf5948c65d0795ad37bbf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46789
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The other two modes are not used by any mainboard, and the code seems to
be copied from older southbridges. As the code looks incorrect, drop it.
Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The dt option `speed_shift_enable` is obsolete now. Drop it.
Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Get rid of legacy pad macros by replacing them with their newer
equivalents.
TEST: TIMELESS-built board images match
Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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I often find myself having to increase the CBFS size so that TianoCore
fits. Raise the default CBFS size to 2 MiB to alleviate this issue.
Change-Id: I871bb95dee55cc5bad68bb6e71f89ddfa4823497
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46488
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's no need to have multiple Kconfig symbols which do the same
thing. Introduce `SUPERIO_NUVOTON_COMMON_COM_A` and update boards to use
the new symbol. To preserve alphabetical order in mainboard Kconfig,
place the new symbol above the Super I/O symbol (instead of below).
Change-Id: Ic0a30b3177a1a535261525638be301ae07c59c14
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46522
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The passive clause is constructed with the past participle, which is
*defined* in this case. Fix all occurrences in AMD vendor code with the
command below.
git grep -l "is define at" src/mainboard/ | xargs sed -i 's/is define at/is defined at/'
Change-Id: I5aa0e6e064410b305aa5f2775271f6a8988da64b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46066
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With a tabulator length of eight spaces, the alignment is the same, but
the other macro definitions are using a space, so do the same for
consistency, better alignment in diff views.
git grep -l -P 'define\tBLD' | xargs sed -i 's,define\tBLD,define BLD,g'
Change-Id: Ib71057c84dc897028cb0ceac29952e67bc541d2e
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I1e0489ec6730760f74102cdd00e4aaa66975d69a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Make output AML file name uniform.
Change-Id: Ic6cac4748a6159c695888b2737ada677d91f4262
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Pictures on the internet show that the Asrock H110M-DVS (Kconfig.name)
only has two DIMM slots. Since the vendor's website advertises support
for dual channel memory, drop the SPD addresses for the second slot of
each channel. The result is the same as several other two-slot boards.
Change-Id: I4b62e9196bfa3a688016399d7e025ca995f3c12c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The DQ and DQS byte maps do not apply to DDR4 configurations, and the
RCOMP resistor and target values are not correct for SKL-S (or KBL-S).
Drop the byte maps and use RCOMP values for the correct platform type.
RCOMP resistor values for all non-socketed platforms are listed in the
Platform Design Guide, and also appear in schematics. For SKL-S, the
RCOMP resistors are on the CPU and their values have been confirmed
by measuring them on an i5-6400, and match the PDG values for SKL-H.
RCOMP target values can be guessed from Intel Document #573387 and some
of them are also present in datasheet volume 1, under DC specifications.
Change-Id: I699d46b9b516be8946367e6d9b24883ae1e78d03
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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This patch moves platform.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify _PIC method present inside
common platform.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Drop GENERIC_SPD_BIN from boards selecting it, despite having no
soldered memory.
Change-Id: Id05fe45007d5662ff9bee326f28470df1206fcff
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45146
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I035b66e749e9a3e1bde13c8ed7ceafeb1edbbfa4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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All boards currently have backlight on either LVDS or eDP.
Change-Id: I878bc7f1ff75a2b82b9556e855aff1d4d03e0268
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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CPU_INTEL_HASWELL is already selected at nb/intel/haswell/Kconfig.
Change-Id: I608286aae72bc740be642a72109472fb235f37bf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I4385fded02e43f3fd8683dd926d81a59c04d3bd9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This allows the Super I/O to know how hot the CPU is.
Change-Id: I9c91136c3bb5aae541bb7ac64bb62be36c3c0b5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Receiver enable results are now saved in flash.
Change-Id: Ib1a985147b081860c58d1649c4e50301b8144b0c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44251
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, SDXC gets enabled by the option ScsSdCardEnabled,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SDXC controller.
All corresponding mainboards were checked if the devicetree
configuration matches the ScsSdCardEnabled setting, and missing
entries were added.
Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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This option has been removed from the parameters structure for Intel
Skylake CPU (commit 9c1c009).
Change-Id: I9dc6649ad693d18fdc85046ebbcc730a17fed0bf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner
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This mainboard has a 18-pin LPC header, where one can plug in a TPM.
Untested, as I don't have a TPM.
Change-Id: I14a159c373987d8b12fde18f327a9eb387c01de8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Use tabs instead of eight (sometimes less) spaces.
Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Some settings are suspicious, and have been annotated with FIXMEs.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I7755867cb92745f542a4261db5dd118ca905612b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Currently HDA gets enabled by the option EnableAzalia, but
this duplicates the devicetree on/off options. Therefore use
the on/off options for the enablement of the HDA controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableAzalia setting.
Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43866
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently eMMC gets enabled by the option ScsEmmcEnabled, but this
duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the eMMC controller.
I checked all corresponding mainboards if the devicetree configuration
matches the ScsEmmcEnabled setting.
Change-Id: I3b86ff6e2f15991fb304b71d90c1b959cb6fcf43
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Currently SMBus gets enabled by the option SmbusEnable, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SMBus controller.
I checked all corresponding mainboards if the devicetree configuration
matches the SmbusEnable setting.
Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Currently LAN gets enabled by the option EnableLan, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableLan setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Currently SATA gets enabled by the option EnableSata, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SATA controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableSata setting.
Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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All boards disable PIRQs. They aren't used on modern OSes anyway.
Change-Id: I1351fd4a3910e8cf2e9afe51dc2e82c7464de403
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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If bit 7 of a PIRQ route is set, it is disabled. Modern OSes don't use
PIRQ routing, so we might as well zero the other bits for consistency.
Tested on Asrock B85M Pro4 with SeaBIOS 1.13.0, still boots.
Change-Id: I78980b9ea5e878a6200df0f6c18c5e7d06a7950a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to the documentation [1], RX Level/Edge Configuration (trig)
and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable
in native mode and BIOS does not need to configure them. Therefore,
there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG
macros. Use PAD_CFG_NF instead and set this fields to 0.
[1] Intel document #549921
[2] Intel document #336067-007US
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: I6a6b745bdaacb1c4fbf032e4ce54cb25a72d790a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43561
Reviewed-by: Michael Niewöhner
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Put them in common code just in case something depends on the values.
Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that libgfxinit has been fixed, trying to enable the Analog port no
longer hangs the system, nor fills the monitor with unreadable garbage.
Tested with linear framebuffer, displays correctly on a 1920x1080 VGA
monitor. Scaling also works when a smaller HDMI monitor is connected as
well. Legacy VGA text mode is also functional on either monitor, too.
Change-Id: Ie2f88edcb7ed1984adebf2af23195767af13654c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43560
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This board uses the in-PCH GbE controller, and its IFD has a GbE region.
Change-Id: Ifc09640b2ebd613d3d5566a13b50d36c11e3c346
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43522
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The ACPI specification, version 2.0 says:
_BFS is an optional control method.
So, remove them. They have been copy-pasted around quite a bit, and do
not do anything useful. Plus, it's deprecated in later ACPI versions.
Change-Id: I9ef21f231dd6051d410ac3a0fe554908409c2fa7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43443
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's no generic way to tell whether a mainboard has an EC or not.
Making Kconfig symbols for these options seems overkill, too. So, just
put them on the devicetree. Also, drop unnecessary assignments when the
board's current value is zero, as the struct defaults to zero already.
Change-Id: If2ebac5fcab278c97dfaf8adc9d1e125888acafe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43129
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If the Intel in-PCH GbE MAC is enabled in the devicetree, then tell MRC
to enable it as well. No one can ever forget to set this option anymore!
Change-Id: I946af36d16c94bb1a0f146604d0329fe6d6ce7e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43128
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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And use it instead of directly writing to the MRC struct.
Change-Id: I7f04db29a08512c1a8b2b2300dba71cb3b84a5c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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Check the PCH's LPC device ID to know the system type instead of relying
on hardcoded numbers. The `get_pch_platform_type` function is MRC-safe.
Change-Id: Icfe7c2dccb7c7a178892ad3a2e34ca93b33b2bb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43124
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Several of these includes are no longer necessary. Get rid of them.
Since "raminit.h" already includes "pei_data.h", we can omit including
the latter for brevity's sake.
Change-Id: Ia7e9dadf87114ca9ea4761b89909ea035cdfc38a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43121
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All mainboards choose the maximum speed of DDR3-1600.
Change-Id: I8863f9d1df950b924f596689ebf1bfda5d317e06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43120
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All mainboards have a non-zero SPD address to implemented DIMM slots.
Knowing this, it is possible to compute the MRC slot population masks
automatically instead of hardcoding the values on each mainboard.
Change-Id: Ia8f369dd1228d53d64471e48700e870e01e77837
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43119
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's no need to redefine common settings.
Change-Id: Ie4ced6efc8119afca070ce86634a3c31c6580d0f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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These settings are the same on all boards. Since the other boards
currently overwrite the struct contents, it doesn't make a difference.
To ease review, the same settings will be dropped from other boards in
separate commits, one board at a time.
Change-Id: I500b7a1d7d97c6976e0c7c10ca491d3875cae22b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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This is what sandybridge does, and if done properly allows factoring out
common settings. Said refactoring will be handled in subsequent commits.
Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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It only contains a pointer to another struct. Flatten it.
Change-Id: Iab427592c332646e032a768719fc380c5794086b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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We only need ACPI for the PS/2 devices. Plus, the NCT6776 ACPI code
makes Windows BSOD with STOP 0xA5 (ACPI_BIOS_ERROR), which is bad.
Change-Id: I4cfad012684264b21284674e8e3713a5d8bb37be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42430
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I6f71419ea23b973b0bedb426e20cb3dc460ef68d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43271
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I00b3af64b6f842d298e91c20ab5f54f0ca3197ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I9b5589d4596eead83a5897b083ccb85ef05a03d5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43270
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Information taken from the boardviews. We are not configuring any GPIO
in bootblock, but we may want to do so in the future.
Change-Id: Iac16f02490adcccd9486718847ca2b1a47f4e6cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42404
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The old values were completely out of whack. Use the same settings as
vendor firmware. The SUPERIO_NUVOTON_NCT6776_COM_A option overwrites
configured settings, so drop it from Kconfig to prevent conflicts.
Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This simplifies things and makes type checking possible.
Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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Instead of passing around a pointer to an array, just write the relevant
registers directly. Note that intel/baskingridge used spaces to indent
line continuations and had to be replaced with tabs to quell Jenkins.
Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This results in a wake from S5 as well. Since the PS/2 keyboard now
works, this behavior is annoying and, therefore, undesired.
Change-Id: I180f17c87df23f2a1bbd5c968c64a4b2bc7d9978
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42431
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows the CPU fan tach signal to reach the Super I/O.
Change-Id: Ibf73d7c7c1951b75ee4e0c731caf951f2c6bfcae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42402
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Otherwise, there are complaints about it from the allocator.
Change-Id: Ibf6124c3720959154d0b9649871f9bf68a912f14
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42401
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIO2 is not used as such, GPIO7 is though. Also relocate GPIO1 settings
under the correct PnP device. Confirmed findings against boardviews.
Change-Id: I4a88ac82d640ca709e7875b4d34b9babb1f2e0a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42400
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I03ca67d748725283ba8382e476d70eb5554f5fb8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42399
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No wonder why the PS/2 keyboard was being detected as a mouse!
Change-Id: I7080c8210d96b079a5c08d98554ed154141086a6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42398
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Only one generic decode range is needed for the HWM.
Change-Id: I964a073efbfaa1d79d3483d59ad04fe674bcb275
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42131
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Comments stating that this was mainboard-specific were very wrong.
Change-Id: I7026ca9c7dabd01b4a0c0549b697e006d5f75eb8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Using proper symbols for base addresses, it is possible to
only define the symbols for base addresses implemented for
the specific platform and executing stage.
Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Use the pre-defined constant address directly.
Change-Id: I29fbc82fffc69b864adb4ddbda1425db98e2e48a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Kconfig 4.17 started using the $(..) syntax for environment variable
expansion while we want to keep expansion to the build system.
Older Kconfig versions (like ours) simply drop the escapes, not
changing the behavior.
While we could let Kconfig expand some of the variables, that only
splits the handling in two places, making debugging harder and
potentially messing with reproducible builds (e.g. when paths end up
in configs), so escape them all.
Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
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New kconfig dislikes unquoted slashes.
Change-Id: Ief242de081071021b9c904a24535d025f6674270
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42480
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ULT only has 4 threads, but we are not changing it here to preserve
binary reproducibility.
Change-Id: I041c5dff2de514244f9c919c4c475cca979c34ce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41842
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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LGA775 CPUs can have at most 4 threads, and Eaglelake supports them.
As this socket is also used by other chipsets, temporarily place this
symbol into the northbridge scope until all chipsets are factored out.
Change-Id: I6e01363d995e135815cc70779e0cd5baf806cf60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Also update autoport accordingly.
Change-Id: I12481363cf0e7afc54e2e339504f70632e8d72e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41839
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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