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2012-11-06Drop redundant CHIP_NAME in mainboard.cKyösti Mälkki
Compose the name from Kconfig strings instead. As the field is for debug print use only, a minor change in the output should do no harm. The strings no longer include word "Mainboard". Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-08-08Cleanup coreboot memory table includesKyösti Mälkki
The includes removed here were previously required for struct lb_memory and lb_add_memory_range(). Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1391 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-08-08Drop HAVE_MAINBOARD_RESOURCESKyösti Mälkki
These existed to provide a hook to add reserved memory regions in the coreboot memory table. Reserved memory are now added as resources. Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-08-02AMD and GFXUMA: move setup_uma_memory() to northbridgeKyösti Mälkki
UMA region can be determined at any time after the amount of RAM is known and before the uma_resource() call. Change-Id: I2a0bf2d3cad55ee70e889c88846f962b7faa0c7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1379 Reviewed-by: Zheng Bao <zheng.bao@amd.com> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-07-31Revert "remove CONFIG_SERIAL_CPU_INIT"Sven Schnelle
This reverts commit 78efc4c36c68b51b3e73acdb721a12ec23ed0369. The broadcast patch was reverted, so this commit should also be reverted. The reason for reverting the broadcast patch: It turned out that sending IPIs via broadcast doesn't work on Sandybridge. We tried to come up with a solution, but didn't found any so far. So revert the code for now until we have a working solution. Change-Id: I05c27dec55fa681f455215be56dcbc5f22808193 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1380 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26Drop mainboard chip.hStefan Reinauer
mainboard_config never worked right, at least not since we've had sconfig. Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that tried to use it anyways. Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1359 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-23AMD and GFXUMA: drop redundant use of lb_add_memory_range()Kyösti Mälkki
Use of uma_resource() in AMD northbridge code created a memory resource marked as reserved. Such resources are removed from system memory in write_coreboot_table(). Change-Id: Ib5e49e851d6622d8ece9d6d612e245b3962b9167 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1233 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-07-16Move setup_uma_memory() to K8 northbridgeKyösti Mälkki
These boards had identical UMA code: amd/dbm690t amd/pistachio technexion/tim5690 technexion/tim8690 The ones below had whitespace or debug level change compared to the one above: kontron/kt690 siemens/sitemp_g1p1 These boards use AMDFAM10 guidelines in code: asrock/939a785gmh amd/mahogany Change-Id: Id7c3f48035727f5847f2d7c3a6e87a3d15582003 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1210 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Move setup_uma_memory() to Agesa Family14 northbridgeKyösti Mälkki
Following boards had identical code: amd/inagua amd/persimmon The following had only whitespace or debug level changes compared to ones above. amd/union_station amd/south_station asrock/e350m1 Change-Id: I11ee46e06e1dd510cba551166189ebcaa144464b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1208 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Define global uma_memory variablesKyösti Mälkki
Use of the uma_memory_base and _size variables is very scattered. Implementation of setup_uma_memory() will appear in each northbridge. It should be possible to do this setup entirely in northbridge code and get rid of the globals in a follow-up. Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-02remove CONFIG_SERIAL_CPU_INITSven Schnelle
The new broadcast code doesn't support serial init - if a CPU needs serial init, this should be handled in the model specific CPU init code. Change-Id: I7cafb0af10d712366819ad0849f9b93558e9d46a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1140 Tested-by: build bot (Jenkins)
2012-05-09Move fadt.c to the cimx sb800 southbridge directory to be shared.Marc Jones
The fadt.c is the same across all the platforms using the sb800 cimx southbridge wrapper. Change-Id: Ifbbfc238732aa46aef96297eaa188b77d27151f3 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1019 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-04-27Move top level pc80 directory to drivers/Stefan Reinauer
There is no reason for this to be a top level directory. Some stuff from lib/ should also be moved to drivers/ Change-Id: I3c2d2e127f7215eadead029cfc7442c22b26814a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/939 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-20Refactor some alignment handlingPatrick Georgi
Made using coccinelle: @@ expression E; @@ -(E + 7) & -8 +ALIGN(E, 8) @@ expression E; @@ -(E + 15) & -16 +ALIGN(E, 16) Change-Id: I071d2c98cd95580d7de21d256c31b6368a3dc70b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/910 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-19Fix messy code in ALIB creationzbao
Fix the copy-paste typo in ALIB table creation. ssdt is useless here. Change-Id: I250066eb5f755275f75c37789ce8760de35b046b Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/885 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-19Leverage the Pstate table created by AGESA.zbao
The name of processor created by AGESA is P00n, whose P is BLDCFG_PROCESSOR_SCOPE_NAME(is 'C' if it is undefined.) and n starts from 0. The dsdt should be aligned with that. This feature has only been tested on persimmon. The changes on all the other boards were propagated. Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/884 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-16ACPI HEST table.zbao
HEST feature starts from ACPI 4.0. HEST is one of four kinds of tables of ACPI Platform Error Interfaces (APEI). In Windows world, APEI is called Windows Hardware Error Architecture (WHEA). APEI consists of four separate tables: 1. Error Record Serialization Table (ERST) 2. BOOT Error Record Table (BERT) 3. Hardware Error Source Table (HEST) 4. Error Injection Table (EINJ) All these 4 tables have the same header as FADT, MADT, etc. They are pointed by RSDP. For the HEST, it contains the error source. The types of them are defined as type description 1. Machine Check Exception (MCE) 2. Corrected Machine Check (CMC) 3. NMI Error 6. PCI Express Root Port AER 7. PCI Express Device AER 8. PCI Express Bridge AER 9. Generic Hardware Error Source Error source types 3, 4, and 5 are reserved for legacy reasons and must not be used. Currently AMD board only provide part of "Machine Check Exception (MCE)" & Corrected Machine Check (CMC)". we need to provide the header of each error source. Other types of Error Sources is in TODO list. Only persimmon is tested. Linux can add HEST feature. The dmesg says, ACPI: HEST 0000000066fe5010 00198 (v03 CORE COREBOOT 00000000 CORE 00000000) ...... HEST: Table parsing has been initialized. No more message is got. Windows can boot with this patch. Havent found a way to test it. Change-Id: I447e7f57b8e8f0433a145a43d0710910afabf00f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/888 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-03-16Rename AMD_AGESA to CPU_AMD_AGESAKyösti Mälkki
Also any CPU_AMD_AGESA_FAMILYxx selects CPU_AMD_AGESA, so remove the explicit selects from the mainboards. Change-Id: I4d71726bccd446b0f4db4e26448b5c91e406a641 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/792 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-08Unify Local APIC address definitionsPatrick Georgi
We used several names for that same value, and hardcoded the value at some more places. They're all LOCAL_APIC_ADDR now (except for lapic specific code that still uses LAPIC_DEFAULT_BASE). Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-22ACPI: More ../../.. removalPatrick Georgi
CPP is ran with src/ as part of its search path, so using <northbridge/...> and the like is safe. Change-Id: I644d60190ac92ef284d5f0b4acf44f7db3c788ee Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/649 Tested-by: build bot (Jenkins)
2012-02-17amd/sb700: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I7a7a1919b7a555156b8da21e8db7dd8f682d68e1 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/661 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-02-17Remove whitespace.Patrick Georgi
Fix issues reported by new lint test. Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/646 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-16SIO: Winbond w83627dhg updateKerry Sheh
1. Stop include c file. 2. W83627dhg Pin 89, Pin 90 are multi function pins, add support to select them to I2C function. Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/565 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-01-18Clean up AMD romstage.c serial outputMarc Jones
This cleans up the strings in romstage.c, removing the ugly "got past". Also, cleaned up comments and some spacing. Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/539 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-18Remove duplicated line of code in AMD wrappers.Marc Jones
This line was unnecessary and was duplicated on several mainboards. Change-Id: I438da05c770ded0bd32256f1c157cabcc383667a Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/541 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-05Fix Fam14 AGESA ACPI table generationMarc Jones
The AGESA wrapper init late call generates the SSDT and other ACPI tables. The call was failing without heap space allocated causing the ASSERT messages in the output. I think are there may still be other issues in integrating the SSDT table with the DSDT, but now it is there to debug. The changes were made in Persimmon and copied to the other Fam14 mainboards. Change-Id: I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/517 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-01-05Clean up AMD Fam14 SSDTMarc Jones
The old SSDT ACPI code would only include the AGESA or the coreboot SSDT. Now include both. AGESA generates the Pstate SSDT and the second coreboot SSDT is for TOM and TOM2. Now, generate the coreboot SSDT instead of patching it. This fixes some ACPI errors in Linux and Windows bluescreens. The Persimmon acpi_tables.c is where the main changes were made and then replicated in the other Fam14 boards. Please test the other mainbords if you have one. Change-Id: I808c863597e024e3e8aeec0821e8618d96cc96a6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/516 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-01-05Fix Fam14 mainboard whitespaceMarc Jones
Fix whitespace and tab issues on fam14 mainbords in preperations for upcoming changes Change-Id: I6d63d428dde0a5d9748027e603b03de25d3be472 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/515 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-01-02F14 mainboard: mptable updateKerry Sheh
Add GNB internal graphic interrupt, correct southbridge hd audio device interrupt. and remove the dead code already commented out. south_station, union_station, inagua, persimmon and e350m1 mainboard are included herein. Change-Id: Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59 Signed-off-by: Kerry Sheh <shekairui@gmail.com> Signed-off-by: Kerry Sheh <kerry.she@amd.com> Reviewed-on: http://review.coreboot.org/451 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-01-02F14 mainboard: update acpi interrupt routing in pic and apic modeKerry Sheh
Add interrupt routing for APU GNB internal Graphic and HD audio device, and other pcie bridge device in GNB. south_station, union_station, inagua, persimmon and e350m1 mainboard are included herein. Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b Signed-off-by: Kerry Sheh <shekairui@gmail.com> Signed-off-by: Kerry Sheh <kerry.she@amd.com> Reviewed-on: http://review.coreboot.org/452 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-12-02Change AMD vendorcode buildKyösti Mälkki
Apply the normal method of recursively including subdirectories for src/vendorcode. Remove redundant references under mainboard and northbridge. Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/468 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01remove trailing whitespaceStefan Reinauer
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-30remove usbdebug.h include from mainboard/romstage codeSven Schnelle
No romstage is supposed to use usbdebug functions/defines directly, so remove all those includes. The usb code is now called and setup from console code. Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/354 Tested-by: build bot (Jenkins)
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n. This might break a couple of boards on runtime, but so far, fixes were quite simple. There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be adapted. Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-23SB800: Hide unused gpp portsKerry Sheh
Add configure option SB_GPP_UNHIDE_PORTS for mainboard to hide/unhide the unused sb800 gpp ports. Certain gpp port should be hidden, if no device was detected and hotplug feature is disabled for such port. Hidden unused ports makes lspci -vvv get more accurate information under Linux. Test on avalue/eax-785e mainboard. Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-19asrock/e350m1: Enable the superio ACPI device in devicetree.cbPeter Stuge
This makes the power_on_after_fail NVRAM option work correctly. Change-Id: I96f05f82d7f133b343cf8d4ef09db50a3db7a83d Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/292 Tested-by: build bot (Jenkins)
2011-10-13Use default table creator macro for all SSDTsStefan Reinauer
Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/262 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Refactor mptable generation some morePatrick Georgi
The last couple of lines of every mptable function were mostly identical. Refactor into common code, a new function mptable_finalize. Coccinelle script: @@ identifier mc; @@ ( -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); | -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); ) Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/246 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Get rid of fixup_virtual_wirePatrick Georgi
As stated in some code files, fixup_virtual_wire was established to avoid touching 200 invocations of the mptable code. Let Coccinelle do it: @@ type T; identifier v; @@ -void fixup_virtual_wire(T v) -{ ... } @@ expression A; identifier v; @@ -v = smp_write_floating_table(A); +v = smp_write_floating_table(A, 0); @@ expression A; identifier v; @@ -v = smp_write_floating_table(A, 0); -fixup_virtual_wire(v); +v = smp_write_floating_table(A, 1); Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/245 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11mainboard: complete the sb800 devicetree even device is offKerry Sheh
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2 enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init will not get called. Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/230 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14Update to Asrock E350m1 for AMD F14 C0efdesign98
This updates the E350m1 Agesa wrapper code to fix an issue with AmdLateRunApTask. It now passes the function parameter through to the Agesa routine. There is also a change to the platform_cfg.h file that makes the definition of BIOS_SIZE dependent on whether or not it was defined earlier. Change-Id: I19942c7d3ecd229a13ef0a69fa7e5b1ea0b909bf Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/139 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-07AMD SB800 southbridge updateKerry She
This patch enables access to the registers of the hardware monitor logical device in the superio via isa ports 0x295/0x296. Previously this was not enabled in the SB8xx LPC device. This is required for initialisation in init_hwm() in src/superio/winbond/w83627hf/superio.c and also by OS-level sensor monitoring such as lm-sensors to access temperature, fan monitoring and control and voltage registers. asrock/e350m1 and advansus/a785e-i mainboard changes are included herein. Change-Id: I2176885549277b335c0c41b48457d09b9b76b703 Signed-off-by: Per Hansen <perh52@runbox.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/159 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07AMD F14 southbridge updateKerry She
This change adds the southbridge related code to support the update of the AMD Family14 cpus to the rec C0 level. Some of the changes reside in mainboard folders but they reference changed files in the southbridge folder so they are included herein. Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-22Update AMD SR5650 and SB700efdesign98
This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-14Move AMD SB800 early clock setup.Scott Duplichan
Move the AMD SB800 early clock setup code that is needed for early serial port operation from mainboard/romstage.c to sb800/bootblock.c. This prevents code duplication and simplifies porting. Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3 Signed-off-by: Scott Duplichan <scott@notabs.org> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/96 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-10ASRock E350M1: ACPI-related BSOD fixScott Duplichan
On installing/starting Windows (tested with Win7 Ultimate) the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error. From Scott Duplichan: To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT must be corrected. The attached patch does this. It uses the older patching method, and not the (possibly preferred) AML generation method. To simplify the patching operation, I moved the AML item 'TOM1' to the start of the SSDT. The patch also includes code to confirm the AML variable TOM1 is at the expected offset before patching. Also tested & working with Linux. Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3 Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/91 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-06-29amd southbirdge sb800 wrapper, pci bridge fixKerry She
sb800 pci bridge SHOULD enabled by default according to the chipset document, but actually not enabled on some mainboard. enable sb800 pci bridge when told to enable in devicetree.cb. tested on ibase persimmon mainboard. Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3 Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/63 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-22Move SB800 clock init earlierScott Duplichan
Committing Scott's e350m1 changes (svn r6585): Move SB800 clock init earlier, Fixes problem where initial serial port output is garbled. Change-Id: If05aa37726b962e8994ee69bf1882fcfae56aa19 Signed-off-by: Scott Duplichan <scott@notabs.org> Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/32 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22Move existing AMD Ffamily14 code to f14 folderefdesign98
This change moves the AMD Family14 cpu Agesa code to the vendorcode/amd/agesa/f14 folder to complete the transition to the family oriented folder structure. Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/52 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22Rename {CPU|NB|SB}/amd/*_wrapper foldersefdesign98
This change renames the cpu/amd/agesa_wrapper, northbridge/ amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and simplify the folder names. There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to append "ull" to a trio of 64-bit hexadecimal constants to allow abuild to run successfully. Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/51 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-20sb800: move spi prefetch and fast read mode to sb bootblock.Stefan Reinauer
So we don't waste time on the first cbfs scan. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> [adapt persimmon with the same change, and work around romcc bug in bootblock code: it doesn't like MEMACCESS[idx] |= value;] Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997 Reviewed-on: http://review.coreboot.org/9 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-20ASRock E350M1: Enable USB3 supportMarshall Buschman
Requires Scott Duplichan's patch for NIC support. Enables required PCIe port for USB3 - does not interfere with normal operations on non-USB3 model. Change-Id: I451bb1b4f799d6485e75fa949933e25e821b65f9 Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/45 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-19ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nicScott Duplichan
Scott Duplichan's patch from the mailing list: sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function once, after determining device 0x15 function enables. 1) Update the asrock e350m1 devicetree.cb to match the hardware. 2) Change the way the sb800 cimx wrapper code works. The original cimx code calls sb800 cimx function sbBeforePciInit() once. When ported to coreboot, the gpp component of this function was called once for each gpp port, as the gpp port's enable/disable state became known. A 05/15/2011 change makes the early gpp code run only once, triggered by processing the 4th gpp port. This method is not general enough because the 4th gpp port is not enabled on all boards. With the current change, the early gpp code runs when the first gpp port is processed. If any gpp ports are enabled, the first must be enabled. Tested with Win7 and linux on asrock e350m1. This change will also affect amd inagua, and has not been tested on that board. Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6 Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/44 Tested-by: build bot (Jenkins) Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2011-06-12ASRock/E350M1: Skip memory clear for boot time reductionMarshall Buschman
Applying Scott's patches to e350m1, svn r6600: Memory clear is not required for non-ECC boards. Change-Id: Ia1a7c926611de72351434cbdc1795ed10bc56ed1 Signed-off-by: Scott Duplichan <scott@notabs.org> Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/20 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-06-07re-indent, so files conform to coding guidelines.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: If840164fa0e2b6349ba920edf06386ba1fe08aab Reviewed-on: http://review.coreboot.org/8 Tested-by: build bot (Jenkins) Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2011-06-04Port persimmon r6594 to e350m1: Cosmetic cleanupPeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6593 to e350m1: Remove unused Kconfig optionsPeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6592 to e350m1: Update GPP port configurationPeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6591 to e350m1: ROM cache earlyMarshall Buschman
Enable rom cache early to reduce boot time. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6590 to e350m1: Work around memory allocation problemMarshall Buschman
Fix memory allocation problem in amdInitLate. Disabled until further debug. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6589 to e350m1: Strip down AGESA optionsMarshall Buschman
Remove some non-essential agesa options to reduce boot time. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6588 to e350m1: VGA framebufferMarshall Buschman
Declare legacy video frame buffer so that Windows generic VGA driver will work. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6587 to e350m1: RTC is not PIIX4 compatibleMarshall Buschman
Declare RTC as not PIIX4 compatible to match AMD hardware. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6586 to e350m1: FADT revisionMarshall Buschman
Make fadt revision match its length. Solves Windows 7 checked build assert. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6584 and r6601 to e350m1: SPI prefetch earlyMarshall Buschman
Enable SPI cacheline prefetch early to reduce boot time. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6583 to e350m1: pstate 0 earlyMarshall Buschman
Switch processor cores to pstate 0 early to reduce boot time. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6582 to e350m1: 33 MHz SPI read earlyMarshall Buschman
Enable 33 MHz fast mode SPI read early to reduce boot time. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6578 and r6596 to e350m1: MMCONF basePeter Stuge
Remove multiple mmconf settings and just use kconfig setting. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6574 to e350m1: MMCONF sizeMarshall Buschman
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6573 to e350m1: VGA, PCI MMIO and SB800 legacyMarshall Buschman
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support. 2) Extend PCI MMIO limit from dfffffff to fecfffff. 3) Add AMD recommended non-posted mapping for SB800 legacy devices. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6572 to e350m1: I/O APIC IDMarshall Buschman
1) Set I/O APIC ID according to BKDG recommendation 2) Correct I/O APIC ID reported by mptable Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20run uart_init() from console_init, just like the other console ↵Stefan Reinauer
initialization functions. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-18* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that valueStefan Reinauer
to unify calls to *_enable_usbdebug() * rename *_enable_usbdebug() to enable_usbdebug() * move enable_usbdebug() to generic romstage console init code and drop it from the individual romstage.c files. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx.Zheng Bao
Since the SB700 has changed to sb7xx_51xx, change legacy name in other mainboard. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01Use subsystem id from devicetree.cb instead of Kconfig and moveSven Schnelle
all boards to the new config scheme. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Following patch fills in the callbacks for PCIe x16 resets. This board uses ↵Rudolf Marek
GPM8,GPM9 as reset toggles. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Correct error in ASRock E350M1 commit that breaks build for ASRock 939a785gmh.Scott Duplichan
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Add support for the ASRock E350M1, an AMD family 14h Fusion board.Scott Duplichan
A video option rom must be added for UMA graphics support. It can be extracted from the supplied UEFI BIOS. ASRock E350M1 support is based on the AMD persimmon project. The major differences are SIO model and DIMM SDP addressing. With this coreboot and seabios, the board can boot DOS from a SATA drive and can boot WinPE from a USB flash drive. I was unable to get Windows setup to run. The board has a socketed SPI flash BIOS chip and a serial port header. The SIO is Nuvoton NCT5572D. Using coreboot's existing Winbond w83627hf is a good enough match to get the serial port and keyboard working. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-24git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6376 ↵Scott Duplichan
2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-16Ooops lets see if this extra comment removal fixes this.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-16Trivial, cleanup of GPIO comments.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16Get mptable OEM/product ID from kconfig variables.Uwe Hermann
We currently use "COREBOOT" unconditionally as the "OEM ID" in our mptable.c files, and hardcode the mainboard name in mptable.c like this: mptable_init(mc, "DK8-HTX ", LAPIC_ADDR); However, the spec says "OEM ID: A string that identifies the manufacturer of the system hardware." (Table 4-2, page 42) so "COREBOOT" doesn't match the spec, we should use the hardware vendor name. Thus, use CONFIG_MAINBOARD_VENDOR which we have already as the "OEM ID" (truncate/fill it to 8 characters as per spec). Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as "product ID", and truncate/fill it to 12 characters as per spec, if needed. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13This patch just turns on the ACPI resume.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11Following patch makes just one fadt.c file. For SB700.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11After this has been brought up many times before, rename src/arch/i386 toStefan Reinauer
src/arch/x86. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-09Deduplicate various ACPI .asl files.Uwe Hermann
The files debug.asl, globutil.asl, and statdef.asl are duplicated in many K8/Fam10h boards. However, they're neither board-specific nor K8/Fam10h-specific nor AMD-specific, so move them to src/arch/i386/acpi. debug.asl contains generic chunks for I/O port 0x80 handling, and debug output over serial port (init COM port, send byte, send string, etc). globutil.asl contains utility methods for string comparison, string length and similar stuff. statdef.asl contains generic ACPI bit definitions / status codes from the ACPI spec (not board- or chipset-specific). This patch was mostly generated by: mkdir src/arch/i386/acpi svn add src/arch/i386/acpi svn cp src/mainboard/amd/dbm690t/acpi/debug.asl src/arch/i386/acpi/ svn cp src/mainboard/amd/dbm690t/acpi/globutil.asl src/arch/i386/acpi/ svn cp src/mainboard/amd/dbm690t/acpi/statdef.asl src/arch/i386/acpi/ cd src/mainboard find . -name debug.asl -exec svn rm {} \; find . -name globutil.asl -exec svn rm {} \; find . -name statdef.asl -exec svn rm {} \; Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08Move "select CACHE_AS_RAM" lines from boards into CPU socket.Uwe Hermann
All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM" into the socket directories, and remove it from the individual boards. Do the same for Intel CPUs/sockets where all boards use CAR. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08second round name simplification. drop the <component>_ prefix.stepan
the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the <componentname>_ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08first round name simplification. drop the <component>_ prefix.stepan
the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the <componentname>_ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-05W83627DHG/W83627EHG fixups for virtual LDNs.Uwe Hermann
W83627DHG: - Add proper "virtual LDN" handling for the LDNs that need it (i.e., those that don't have their "enable" bit in bit 0 of the 0x30 register). - Fix various I/O masks in the pnp_dev_info[] array as per datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN. W83627EHG: - Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was mostly implemented already, though). - Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN. Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt for the virtual LDNs. include/device/pnp.h: Add comment that 'function' (which refers to the LDN and should probably be renamed later) has to be at least 16 bits wide. In theory LDNs could use u8, but due to the virtual LDN info being encoded in the "high byte" of 'function' it must be at least u16. asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV. ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial port 1 in this case) to avoid confusion. The global registers manipulated there are accessible from any LDN. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-04Following patch removes the cut-and-paste stuff from Mahagony and fixes the ↵Rudolf Marek
_CRS object to make it work (same code as on M2V-MX SE) Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-30The patch just make the power LED on.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-30Fix the SPD to channel mapping. Please note that there is something wrong ↵Rudolf Marek
with UMA. Single channel (in slot DDR1 and DDR3) produces strange artefacts on screen (and hang) Dual Channel (in DDR1 and DDR2 aka blue slot) - works nice All slots populated - same case as Single channel - must be something wrong with UMA. Tested with 2x 512MB CAS 2.5 DDR400 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Simplify a few code chunks, fix whitespace and indentation.Uwe Hermann
Also, remove some less useful comments, some dead code / unused functions. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Drop excessive whitespace randomly sprinkled in romstage.c files.Uwe Hermann
Also drop some dead or useless code snippets. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Convert boards to use mptable_write_buses.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20Unify DIMM SPD addressing. For Geode, change thePatrick Georgi
addressing scheme to match the rest of the tree (0x50 instead of 0xa0). abuild tested. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Eliminate SET_NB_CFG_54 option. There was no board thatPatrick Georgi
deselected it, and very likely there won't ever be any hardware that requires it deselected. Keep the "selected" code path around, leading to no functional change. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17This problem was introduced withTobias Diedrich
http://tracker.coreboot.org/trac/coreboot/changeset/3953 Note that all corresponding DSDTs only ever check TOM2 against 0. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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