Age | Commit message (Collapse) | Author | |
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2024-08-26 | nb/intel/haswell: Move SPD addresses to devicetree | Keith Hui | |
Introduce a sandybridge-style devicetree setting for SPD addresses, and use it instead of runtime code in mb_get_spd_map() for all haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all boards except google/slippy. Patch also covers recently added Z97 boards using Broadwell MRC. Also update util/autoport to match. abuild passes for all affected boards. autoport builds, but otherwise untested. Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | |||
2024-07-03 | mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell) | Jan Philipp Groß | |
This is a rudimentary port of this board. It was done with Haswell Autoport, wherein some adjustments for Broadwell were made (Thanks to Angel Pons!). The VBT was copied from /sys/kernel/debug/dri/1/i915_vbt on version 2.20 of the vendor firmware. Working: - Broadwell MRC.bin - S3 suspend and resume - All DIMM slots - Libgfxinit - HDMI-Out Port - DVI-I Port (including passive DVI to VGA adapter) - USB 2.0 Ports - USB 3.1 Gen1 - RJ-45 LAN Port - SATA3 6.0 Gb/s Connectors - m.2 PCIe SSD - mPCIe WiFi slot - x16 PCIe slot - USB 3.1 Gen1 Header - Front Panel Audio Connector - edk2 Not yet tested: - SATA Express 10 Gb/s Connector - HDMI-In Port - DisplayPort 1.2 - Optical SPDIF Out Port - PS/2 Mouse/Keyboard Port - USB 2.0 Headers Not working: - Broadwell CPUs, see commit f5105313cf69 (mb/asrock/z97_extreme6: Add new mainboard) Special thanks to Angel Pons for guiding me through the process of porting this board and pushing it to Gerrit! Change-Id: I3b940e9281814e8360900221714c0dfa3ae39540 Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82760 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> |