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2024-08-26mb/*/*/early_init.c: Remove unused included southbridgeElyes Haouas
Change-Id: Ia3fda208f5cb2e0d8a1e4da2c4392bc0f326d1ed Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84076 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08mb/*: Remove old USB configurations from SNB/bd82x6x boardsKeith Hui
Remove USB configurations and data structures from northbridge devicetree (SNB+MRC boards) and bootblock/romstage C code (native-only SNB boards). All USB configurations are drawn from southbridge devicetree going forward. Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07mb/*: Copy bd82x6x boards' USB port config into devicetreeKeith Hui
For mainboards using southbridge/intel/bd82x6x, copy the contents of mainboard_usb_ports array into southbridge devicetree. In-line comments are maintained. Boards also capable of using MRC raminit are done in a separate patch. Change-Id: Ia8a967eb3466106f3a34e024260e13d02f449a25 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81879 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07mb/**/hda_verb: Use `AZALIA_PIN_CFG_NC(0)`Angel Pons
Replace `0x411111f0` with `AZALIA_PIN_CFG_NC(0)`, which evaluates to the same value and conveys additional information to the reader. Done with a bulk search and replace operation. Change-Id: Ibd84daec017bc1ab1ee4edd906fda80231c134cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18mb/*: Add SPDX headers for cmos.default filesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib7beed7218f317bc2352b65a6191ef1cdaa0742d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2024-02-18mb/51nb to mb/bytedance: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: I71dc3dd270b9a61c86b59031f898af37f0fea345 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80590 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/51nb to mb/gigabyte: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I422cb475723006ca42be93508fb0bf4b1e4e84d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80104 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-13mb/*: Update SPD mapping for sandybridge boardsKeith Hui
Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree. Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping. Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-30mb/asrock/h77pro4-m: Make onboard NIC a child device below PCIe port 6Kevin Keijzer
The Realtek RTL8111E NIC is currently not defined as a child device, resulting in the on_board flag not being set to 1. This means that Linux / udev will call the device enp4s0 rather than eno0, as is appropriate for on-board ethernet devices. This patch defines the NIC as a child device of PCIe port 6, so that it's properly defined as an on-board device. Change-Id: I2e1b65e4d27852297a739e332c52c15a8c81b858 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74090 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-18mb/asrock/h77pro4-m: Use VBT provided by Linux' debugfsMichael Büchler
The current VBT causes problems with Windows 10. Once the Intel driver is used instead of the generic graphics driver, the display turns off although the system keeps running normally. Linux has no issues. It had been extracted from the vendor video BIOS, which in turn had been extracted from the vendor firmware. This change replaces the VBT with one that was dumped through debugfs and the drm/i915 driver in Linux, booted from the vendor firmware at version 2.10 (beta). It fixes the issue with the Intel graphics driver on Windows 10. Change-Id: Icbb3950b37dad5ed308f3bafb73b71859227d26b Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73711 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04mb/*: Replace SNB PCI devices with references from chipset.cbArthur Heymans
Removing default on/off from mainboard devicetrees is left as a follow-up. Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-30nb/intel/sandybridge: Add a chipset devicetreeArthur Heymans
This only moves CPU configuration to a common place. Other PCI devices can be done in follow-ups. Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13src/mb: Update unlicensable files with the CC-PDDC SPDX IDMartin Roth
These files contain no creative content, and therefore have no copyright. This effectively means that they are in the public domain. This commit updates the unlicensable empty (and effectively empty) files with the CC-PDDX identifier for license compliance scanning. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I0b76921a32e482b6aed154dddaba368f29ac2207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66497 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-23mb/asrock: Add ASRock H77 Pro4-M mainboardMichael Büchler
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM. The port was initially done with autoport. It is quite similar to the ASRock B75 Pro3-M which is already supported by coreboot. Working: - Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) - Native RAM initialization with four DIMMs of two different types - PS/2 combined port (mouse or keyboard) - Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) - PCIe graphics in the PEG slot - All three additional PCIe slots - All rear and internal USB2 ports - All rear and internal USB3 ports with reasonable transfer rates - All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s) - All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s) - Rear eSATA connector (multiplexed with one ASM1061 port) - Console output on the serial port of the Super I/O - SeaBIOS 1.15.0 to boot slackware64 - SeaBIOS 1.15.0 to boot Windows 10 (needs VGA BIOS) - Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`) - External flashing with flashrom-1.2 and a Raspberry Pi 1 - S3 suspend/resume from either Linux or Windows 10 Not working: - Booting from the two SATA ports provided by the ASM1061 - Automatic fan control with the NCT6776D Super I/O Untested: - VBT (it is included, though) - Infrared header Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 18:57:22 +0000