coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-06-09	mb/asrock/g41c-gs: Rename the board to G41C-GS R2.0 (g41c-gs_r2_0).	Bill XIE
	The supported "G41C-GS" with a nuvoton nct6776 superio is actually G41C-GS R2.0, which is different with the more easily-found revision G41C-GS (R1.0) with Winbond W83627DHG superio, and should be ported separately. Photos for the two revision: R1.0: https://web.archive.org/web/20160915160553/http://www.asrock.com/mb/photo/G41C-GS(L1).jpg R2.0: https://web.archive.org/web/20160717203810/http://www.asrock.com/mb/photo/G41C-GS%20R2.0(L2).jpg Change-Id: If60a694bcf0652ab32c0ac75ceec7e27e11fe9eb Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/19980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-02	Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG	Nico Huber
	* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER. * Let drivers select it if they are in charge. * Don't select it on the mainboard level if a driver handles it. Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-13	mainboard: Add ASRock G41C-GS	Arthur Heymans
	Start-point is Gigabyte GA-G41M-ES2L. This board features a G41 northbridge and an ICH7 southbridge. This board has slots for both DDR2 and DDR3 (cannot run concurrently though) but only DDR2 is implemented in coreboot. The SPI flash resides in a DIP-8 socket. Tested and working: * DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky with assymetric dimm setups); * 3,5" IDE; * SATA; * PCIe x16 (with some patches up for review); * Uart, PS2 Keyboard; * USB, ethernet, audio; * Native graphic init; * Fan control; * Reboot, poweroff, S3 resume; * Flashrom (vendor and coreboot). Tested but fails: * DDR3 (not implemented in coreboot). Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0. Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>