coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2016-08-14	src/mainboard: Capitalize ROM, RAM, CPU and APIC	Elyes HAOUAS
2016-07-31	Remove extra newlines from the end of all coreboot files.	Martin Roth
2016-06-04	AGESA boards: Split dispatcher to romstage and ramstage	Kyösti Mälkki
2016-05-10	AGESA boards: Relocate platform memory config	Kyösti Mälkki
2015-11-02	asrock/e350m1: Add ACPI S3 support	Kyösti Mälkki
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-06-08	Remove empty lines at end of file	Elyes HAOUAS
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-05-10	AGESA: Drop unused AGESA_MEM_TABLE	Kyösti Mälkki
2015-01-06	Remove AMD's "Release Content" doxygen from coreboot files	Martin Roth
2014-07-18	mainboard: Make use of ARRAY_SIZE in buildOpts.c on AGESA platforms	Edward O'Callaghan
2014-07-08	mainboard: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2013-04-02	ASRock E350M1: buildOpts.c: Add missing memory related defines	Paul Menzel
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2011-11-01	remove trailing whitespace	Stefan Reinauer
2011-06-04	Port persimmon r6589 to e350m1: Strip down AGESA options	Marshall Buschman
2011-02-24	git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6376 2b7e53f0-3cfb-0310-b3e...	Scott Duplichan