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This is abuild-tested by me.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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code to use it. That makes the code more readable and also less
error-prone.
Abuild tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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targets/*/*/Makefile
targets/*/*/normal/Makefile
targets/*/*/fallback/Makefile
to use a common copy of romcc, and to leave this compiler untouched by
'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ .
'make clean' in targets/*/*/ will clean romcc.
Thanks to Mats for the initial idea and implementation of a tool to do
this. This patch has almost the same behaviour as the original tool
without having to run the tool each time.
Tested for abuild-friendliness.
The patch saves ~10-12 seconds for every target using romcc. For a full
abuild run, this is ~20% time saved.
For the first 38 abuild targets, total build time is down to 13m24s
instead of 16m22s on my machine.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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DISTRO_CFLAGS were not being
included on the CC line for cache_as_ram_auto.c
Tested on ubuntu, where formerly it failed.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Options.lb file that already had a "uses CONFIG_COMPRESSED_PAYLOAD_LZMA"
line in it.
I figure that only adding it to the files that already have support
for LZMA payloads makes sure I don't break anything.
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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(Patch 2, refs #14)
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and leaving enough room for a real payload (not /dev/null)
This is a wonderful example why "uses" sucks.
* add Config-abuild.lb for those boards that dont build with
the default settings and a real payload:
arima/hdama, amd/quartet, amd/serengeti_cheetah, ibm/e326
* if lzma is installed and a real payload is used, try compressing
it.
* fix a small bug in "abuild --help"
This patch is acked by me because its due to infrastructural changes only.
Flames welcome.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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same format for all CHIP_NAME() entries in LinuxBIOS (Closes #20).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@linuxbios.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and (hopefully) the correct canonical name of the vendor and board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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will then rename the src/superio/NSC directory to src/superio/nsc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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https://openbios.org/roundup/linuxbios/issue44
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1201_ht_bus0_dev0_fidvid_mb.diff part 1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Special version for HDAMA rev G with 33Mhz test and reboot out.
- Support for CPU rev E, dual core, memory hoisting,
- corrected an SST flashing problem. Kernel bug work around (NUMA)
- added a Kernel bug work around for assigning CPU's to memory.
r2@gog: svnadmin | 2005-08-03 08:47:54 -0600
Create local LNXI branch
r1110@gog: jschildt | 2005-08-09 10:35:51 -0600
- Merge from Tom Zimmerman's additions to the hdama code for dual core
and 33Mhz fix.
r1111@gog: jschildt | 2005-08-09 11:07:11 -0600
Stable Release tag for HDAMA-1.1.8.10 and HDAMA-1.1.8.10LANL
r1112@gog: jschildt | 2005-08-09 15:09:32 -0600
- temporarily removing hdama tag to update to public repository. Will
reset tag after update.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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1. x86_setup_mtrr take address bit.
2. generic ht, pcix, pcie beidge...
3. scan bus and reset_bus
4. ht read ctrl to decide if the ht chain
is ready
5. Intel e7520 and e7525 support
6. new ich5r support
7. intel sb 6300 support.
yhlu patch
1. split x86_setup_mtrrs to fixed and var
2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
3. in_conherent.c K8_SCAN_PCI_BUS
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
write_pirq_routing_table for x86
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
cache_as_ram for AMD and some intel
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Li-Ta Lo <ollie@lanl.gov>
Onboard VGA for HDAMA
Added onboard VGA support for Arima/HDAMA
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Li-Ta Lo <ollie@lanl.gov>
emulator update
x96emu update from Paulo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Li-Ta Lo <ollie@lanl.gov>
emulator update
Correction to the reduce emulator from Paulo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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complex expression.
crt0.S.lb: Modified so that it is safe to include console.inc
console.c: Added print_debug_ and frieds which are non inline variants of the normal console functions
div64.h: Only include limits.h if ULONG_MAX is not defined and define ULONG_MAX on ppc
socket_754/Config.lb Conditionally set config chip.h
socket_940.c We don't need and #if CONFIG_CHIP_NAME we won't be linked in if there are no references.
slot_2/chip.h: The operations struct need to be spelled cpu_intelt_slot_2_ops
slot_2/slot2.c: The same spelling fix
socket_mPGA603/chip.h: again
socket_mPGA603/socket_mPGA603_400Mhz.c: and again
socket_mPGA604_533Mhz/Config.lb: Conditionally defing CONFIG_CHIP_NAME
socket_mPGA604_800Mhz/chip.h: Another spelling fix
socket_mPGA604_800Mhz.c and again
via/model_centaur/model_centaur_init.c: It's not an intel CPU so don't worry about Intel microcode uptdates
earlymtrr.c: Remove work around for older versions of romcc
pci_ids.h: More ids.
malloc.c: We don't need string.h any longer
uart8250.c: Be consistent when delcaring functions static inline
arima/hdama/mptable.c: Cleanup to be a little more consistent
amdk8/coherent_ht.c:
- Talk about nodes not cpus (In preparation for dual cores)
- Remove clear_temp_row (as it is no longer needed)
- Demoted the failure messages to spew.
- Modified to gracefully handle failure (It should work now if cpus are removed)
- Handle the non-SMP case in verify_mp_capabilities
- Add clear_dead_routes which replaces clear_temp_row and does more
- Reorganize setup_coherent_ht_domain to cleanly handle failure.
- incoherent_ht.c: Clean up the indenation a little.
i8259.c: remove blank lines at the start of the file.
keyboard.c: Make pc_keyboard_init static
ramtest.c: Add a print out limiter, and cleanup the printout a little.
amd8111/Config.lb: Mention amd8111_smbus.c
amd8111_usb.c: Call the structure usb_ops not smbus_ops.
NSC/pc97307/chip.h: Fix spelling issue
pc97307/superio.c: Use &ops no &pnp_ops.
w83627hf/suerio.c: ditto
w83627thf/suerio.c: ditto
buildrom.c: Use braces around the body of a for loop. It's more maintainable.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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CROSS_COMPILE
CC
HOSTCC
OBJCOPY
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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chip for the amdk8/root_complex
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
enabled. All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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ram linuxbios_ram instead of linuxbios_c and linuxbios_payload...
- Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86
- ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB.
- Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work.
- Start using romcc's built in preprocessor (This will simplify header compiler checks)
- Add helper functions for examining all of the resources
- Remove debug strings from chip.h
- Add llshell to src/arch/i386/llshell (Sometime later I can try it...)
- Add the ability to catch exceptions on x86
- Add gdb_stub support to x86
- Removed old cpu options
- Added an option so we can detect movnti support
- Remove some duplicate definitions from pci_ids.h
- Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic
- Minor romcc bug fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- mem.h and sizeram.h and all includes killed because the are no longer needed.
- linuxbios_table.c updated to directly look at the device tree for occupied memory areas.
- first very incomplete stab a converting the ppc code to work with the dynamic device tree
- Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources).
- First stab at Pentium-M support
- add part/init_timer.h making init_timer conditional until there is a better way of handling it.
- Converted all of the x86 sizeram to northbridge set_resources functions.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.
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- Fix the hdama Config.lb to not longer use the link keywords oops,
and instead to have it nest everything properly.
- Update config.g to not support the link keyword
- update config.g to not support northbridge/southbridge/cpu/pmc noise words
we can just use chip now.
- Remove old link handling from the code
- Detect and handle duplicate paths so we generate one device with multiple links
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Things are close but not quite there yet.
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mechanisms should
be in place but don't expect anything to quite work yet.
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- Updated the romcc version in Config.lb
- Fixed type sizes in romcc_io.h and io.h inl() returning a byte was nasty
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Although it is not used currently, misuse of terminolog is still a misuse.
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Unified AMD K8 reset function that can be customized via mainboard Config.lb
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on all amd64 motherboards, so it moved to the amdk8 specific code.
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- Reworked pnp superio device support. Now complete superio support is less than 100 lines.
- Added support for hard coding resource assignments in Config.lb
- Minor bug fixes to romcc
- Initial support for catching the x86 processor BIST error codes. I've only seen
this trigger once in production during a very suspcious reset but...
- added raminit_test to test the code paths in raminit.c for the Opteron
- Removed the IORESOURCE_SET bit and added IORESOURCE_ASSIGNED and IORESOURCE_STORED
so we can tell what we have really done.
- Added generic AGP/IOMMU setting code to x86
- Added an implementation of memmove and removed reserved identifiers from memcpy
- Added minimal support for booting on pre b3 stepping K8 cores
- Moved the checksum on amd8111 boards because our default location was on top of
extended RTC registers
- On the Hdama added support for enabling i2c hub so we can get at the temperature
sensors. Not that i2c bus was implemented well enough to make that useful.
- Redid the Opteron port so we should only need one reset and most of memory initialization
is done in cpu_fixup. This is much, much faster.
- Attempted to make the VGA IO region assigment work. The code seems to work now...
- Redid the error handling in amdk8/raminit.c to distinguish between a bad value
and a smbus error, and moved memory clearing out to cpufixup.
- Removed CONFIG_KEYBOARD as it was useless. See pc87360/superio.c for how to
setup a legacy keyboard properly.
- Reworked the register values for standard hardware, moving the defintions from
chip.h into the headers of the initialization routines. This is much saner
and is actually implemented.
- Made the hdama port an under clockers BIOS. I debuged so many interesting problems.
- On amd8111_lpc added setup of architectural/legacy hardware
- Enabled PCI error reporting as much as possible.
- Enhanded build_opt_tbl to generate a header of the cmos option locations so
that romcc compiled code can query the cmos options.
- In romcc gracefully handle function names that degenerate into function pointers
- Bumped the version to 1.1.6 as we are getting closer to 2.0
TODO finish optimizing the HT links of non dual boards
TODO make all Opteron board work again
TODO convert all superio devices to use the new helpers
TODO convert the via/epia to freebios2 conventions
TODO cpu fixup/setup by cpu type
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- Support for compiling romcc on non x86 platforms
- new romc options -msse and -mmmx for specifying extra registers to use
- Bug fixes to device the device disable/enable framework and an amd8111 implementation
- Move the link specification to the chip specification instead of the path
- Allow specifying devices with internal bridges.
- Initial via epia support
- Opteron errata fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Major restructuring of hypertransport handling.
Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically
Updates to hard_reset handling when resetting because of the need to change hypertransport link
speeds and widths.
(a) No longer assume the boot is good just because we get to a hard reset point.
(b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the
boot counter.
Updates to arima/hdama mptable so it tracks the new bus numbers
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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* subtractive resources
* merging with the static device tree
* more device types than just pci
- The piece to watch out for is the new enable_resources method that was needed in all of the drivers
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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for paths
- Renamed some configuration variables
SMP -> CONFIG_SMP
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
- Removed some dead configuration variables
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
SMP -> CONFIG_SMP
FINAL_MAINBOARD_FIXUP
SIO_BASE
SIO_SYSTEM_CLK_INPUT
NO_KEYBOARD
USE_NORMAL_IMAGE
SERIAL_CONSOLE
USE_ELF_BOOT
ENABLE_FIXED_AND_VARIABLE_MTRRS
START_CPU_SEG
DISABLE_WATCHDOG
ENABLE_IOMMU
AMD8111_DEV
- Removed some assembly files that are no longer needed
killed src/southbridge/amd/amd8111/smbus.inc
killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc
killed src/ram/ramtest.inc
- Updates to config.g so that it works more reliably and has initial support
for paths
- Renamed some configuration variables
SMP -> CONFIG_SMP
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
- Removed some dead configuration variables
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
SMP -> CONFIG_SMP
FINAL_MAINBOARD_FIXUP
SIO_BASE
SIO_SYSTEM_CLK_INPUT
NO_KEYBOARD
USE_NORMAL_IMAGE
SERIAL_CONSOLE
USE_ELF_BOOT
ENABLE_FIXED_AND_VARIABLE_MTRRS
START_CPU_SEG
DISABLE_WATCHDOG
ENABLE_IOMMU
AMD8111_DEV
- Removed some assembly files that are no longer needed
killed src/southbridge/amd/amd8111/smbus.inc
killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc
killed src/ram/ramtest.inc
killed src/sdram/generic_dump_spd.inc
killed src/sdram/generic_dump_spd.inc
- Updated the arima/hdama to build with the new configuration system
- Updated config.g to list all of the variables with make echo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Moving tyan resource map to tyan directory. Making IOMMU for hammer choosable
via ENABLE_IOMMU
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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cpu of a certain type and to eliminate the
cpu p5
cpu p6
cpu k7
nonsense in the old config files.
Next step is to hook into Eric's pci device stuff.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Bump up debugging messages and reduce the size of memory test until that is
running correctly.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- SMP cleanups (remove SMP only use CONFIG_SMP)
- Minor tweaks to romcc to keep it from taking forever compiling
- failover fixes
- Get a good implementation of k8_cpufixup and sizeram for the opteron
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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* remove dead code from coherent_ht.c
* add ldtstop code for link speed changes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Changes to allow more code to be compiled both ways
- Working SMP support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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due to different routing defaults of different boards.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Remove some debugging code from auto.c
- Update coeherent_ht.c so we get the proper broadcast routes.
- Fix the dram probing code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Add initial support for the amd8131
- Update the mptable to something possible
- hdama/Config add the amd8131 southbridge
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- romcc_io.h Add include guards.
- hdama/Config nothing really but I have been moving the setting back and forth between 1 and 2 cpus
- auto.c Changed the enabled debugging comments. This almost works with 2 cpus
- coherent_ht.c First pass at getting this right. It can now find 2 cpus and place them
in some semblance of a working state.
- raminit.c Fix problems with 4GB of ram. Disable some of the debugging code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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part-specific struct into the tree.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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I set USE_FALLBACK_IMAGE to 1 in the top-level Config, but when it is tested
in arima/hdama/Config.lb, it is acting as though it is zero.
Also added a print command so it is easier to trace 'if' behavior.
Usage:
print "string"
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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more fixes to various Config.lb
one last problem and we're there
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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we need to get rid of yappsrt.pyc
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@906 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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