| Age | Commit message (Collapse) | Author |
|---|
|
Change-Id: Iba8b8d33e1f10e28745234988d97d4fafd04c798
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
All thse Option.*Install.h files are about configuring
what eventually is referenced in the final libagesa
build. It's self-contained so isolate these together
with PlatformInstall.h to hide them from rest of
the build.
Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I9cb63ff58900a39d7cd8e3da2b9a9a95c2a41a69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I1a96b1c6181cd657d7aee82370ef86acd688cc94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
For boards with cimx/sb800, mainboards defined only empty
stubs. Reset functionality is handled as BiosCallout.
For amd/inagua, the defined function was actually initial
GPIO programming.
For cimx/sb700, function had prototypes but no callers.
For cimx/sb900, everything was commented out already.
Change-Id: I936feb4fc41d903078620c919a733bb9f39c3efb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I84c70aa04ab556a3898d3525f7b9aab85812f61d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Vendorcode for f15 also has f10 support, so
AMD_AGESA_FAMILY_10 was never selected.
Change-Id: I9a026c36ace88f1110a52d7e24d3e6ab36508932
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: I706de64ae5d940df70701c8b9dd717f8e212cd0e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I09fe0e903a1241212f81e2a897898356a7e372a9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Id2ef3e5aa0ea3f6e714eda6d9dbdf62fb96c0a74
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Ie76291a8e227e49aae6fc6339cec2009ebd67fff
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Move the fchec.h files, which do not seem mainboard specific, out of
the mainboard directories into the southbridge/soc directories.
Change-Id: Idd271c6ab618aa4badf81c702212e7de35317021
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
This is not specific to a board but the binary IMC firmware
used on the platform. Also remove unused IMSP and IMWK methods.
Change-Id: I80026bca55f5ba236c080bcd882fc374559942e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
While at it, replace LibAmdMemFill() with memset().
Change-Id: I770cab446add8f305f02e365e7c9763df88cd958
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21192
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It was not intentional to change oem_fan_control() to non-static
with commit
23e5ba9 binarypi mainboards: Clean up IS_ENABLED fan control
Every platform except bettong had its own static version of
oem_fan_control, so remove the definition of oem_fan_control from imc.h,
and move it out of imc.c into bettong's BiosCallOuts.c.
Change-Id: Ie95ac1fd3a57259bb35796903aa8753ef0e70d70
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21189
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around
the imc.h includes. Convert from #if to if() for all fan control
setup code. Where necessary, make functions non-static to match the
prototypes in imc.h.
Change-Id: If88af42d00227285931829441909a982fc292b2b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around
the imc.h includes. Convert all #if to if() for fan control setup.
Change-Id: I04a9fbbf6f64f45e1a0b544267bfe840ce7fa1d9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Convert from #if to if().
Change-Id: Icf6db485735cb8bbadb3e742a079d0bafaacd79c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I7194eb910cccc454c5f20c23629ff2a45b1a9079
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I3730bf87030b7e20991e1de00d2024e4b02f4c19
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I646a8f4cfc1df8648a72e58814c36ea66b48e9d7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Iac0998a56b4e297c512fcba98d3dbb4253c9b526
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Sync file with southbridge/amd/common/sleepstates.asl.
SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
Change-Id: I674953f1a5add74e16ddd84c252e8d21501ffefd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Note that against the specs, these definitions repeat
the sleep type also in the reserved fields 3 and 4.
For consistency, don't fix it here now.
Entry for \_S3 is now masked off if HAVE_ACPI_RESUME=n.
Change-Id: Icdc4c81d07fe7a99d5b0f8fa23e9443f58a40ab9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
Note that all boards incorrectly had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
Change-Id: Ia948becff079383cbf861468da9e8a3ebbf213cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
SSFG was meant to be used as a mask to enable sleep states
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
State _S3 is now set conditionally if HAVE_ACPI_RESUME=y.
For pi/hudson this had been fixed already preprocessor.
Note that all boards had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
States _S1 and _S2 still appear enabled in ASL/AML
but may not actually work.
TEST: 'cat /sys/power/state' and notice choice 'mem' was
removed from the list of available sleep states.
Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Change-Id: I5e7890aafbc8c80716ee49690e306482a482a863
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20573
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
|
|
A decision has been made that boards with LATE_CBMEM_INIT
will be dropped from coreboot master starting with next
release scheduled for October 2017.
As existing implementation of CAR teardown in AGESA can only
do either EARLY_CBMEM_INIT or ACPI S3 support, choose the former.
ACPI S3 support may be brought back at a later date for
these platforms but that requires fair amount of work fixing
the MTRR issues causing low-memory corruptions.
Change-Id: I5d21cf6cbe02ded67566d37651c2062b436739a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Simplify funciton names and remove reference to hudson in stoneyridge.
The southbridge in Stoney Ridge is Kern and hudson naming is
no longer accurate.
BUG=b:62200157
BRANCH=none
TEST=Build and booted on Kahlee.
Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
We define AGESA_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Move the mainboard MADT tables to generic soc ACPI code.
Change-Id: I49fb55b1315da8fe65421b43fc4312ed588d5ecb
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20277
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build. The .S files
are mostly duplicated code from the old cache_as_ram.inc file.
The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.
Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S. Drop the BIST check like other devices.
Move InitReset and InitEarly to bootblock. These AGESA entry
points set some default settings, and release/recapture the
AP cores. There are currently some early dependencies on
InitReset. Future work should include:
* Pull the necessary functionality from InitReset into bootblock
* Move InitReset and InitEarly to car_stage_entry() and out of
bootblock
- Add a mechanism for the BSP to give the APs an address
to call and skip most of bootblock and verstage (when
available) (1)
- Reunify BiosCallOuts.c and OemCustomize.c
(1) During the InitReset call, the BSP enables the APs by setting
core enable bits in F18F0x1DC and APs begin fetching/executing
from the reset vector. The BSP waits for all APs to also
reach InitReset, where they enter an endless loop. The BSP
sends a command to them to execute a HLT instruction and the
BSP eventually returns from InitReset. The goal would be to
preserve this process but prevent APs from rerunning early
code.
Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Fix the OEM settings for two ports. Fix and clarify comments to
reflect Rev. B of the board design.
Change-Id: I2812ea5945f67229872e78041c771606047bbbec
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20744
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Convert from #if to if().
Change-Id: I50b3ed9ecd5947ff625536b196d90ebd4e8f1c56
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Convert from #if to if().
Change-Id: I7c149856da22b72d2a83bd7f06d031df328dbb35
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The romstage for CS5536 platforms were including early_smbus.c and
early_setup.c. Build these into romstage from the makefile, and remove
the #includes.
Add a Kconfig option for platforms that do not use the
early smbus code.
Change-Id: I2e6a9cd859292b4dd4720b547d1ff0bbb6c319cf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I67c682f79834bed334f26a4c7473eaf463262a85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: Ie17cc7367fc8561e2ecb357d4f8282c1cd444b7f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Calling disable_cache_as_ram() with valuables in stack is not
a stable solution, as per documentation AMD_DISABLE_STACK
should destroy stack in cache.
While we still preserve cache contents (there is wbinvd deep
inside AMD_DISABLE_STACK macro), we now actually do a stack
switch and much more closely meet the specification of CAR
teardown sequence in AGESA specifications.
We now somewhat incorrectly include files from agesa/ tree,
but the whole agesawrapper.c file removal will address the
issue of overall directory layout.
Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: Id20a49385aeb336461acd0bd186a4ab7f3fb95b8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Essentially squashes following commits from AGESA side.
45ff9cb AGESA: Reduce typecasting in heapmanager calls
bceccec AGESA: Handle HEAP_CALLOUT_RUNTIME allocation more cleanly
4240277 AGESA: Adjust heap location for S3 resume path
424c639 AGESA: Refactor S3 support functions
50e6daf AGESA: Log heap initialisation
da74041 AGESA: Move heap allocator declarations
c74b53f AGESA: Reduce SPI use by 24kB for S3 support
b1fcbf3 AGESA: Separate HeapManager declarations from BiosCallOuts
f728408 AGESA: Split S3 backup in CBMEM
82fbda7 AGESA: Use same HeapManager for all BiosCallOuts
Change-Id: I537bd05a3e06ff6896f1ac8be93eed5321ca472b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I370285aa52776170a32b6dd36c0eef74eea9400c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
We remove this particular header file already while remaining
of include fixes is longterm and pending work.
Change-Id: I869d426c1344290a00e2df60e07e9a4a3ae26887
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: I63c6febf8ba953a642fd7b04a555a4c6704abc79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: Icca8bac5e67f83dfc5a8f5ef1cb87c6432e0a236
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: I6ccbbee00aab947079c3471fcf83ae9a66c01d59
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: I6ede71ec660678bb5f77693a9095aa0f198e4e26
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
In the code we do the following in a number of places
to pre-initialize an array with a certain value before
overwriting some of the array with other values:
u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
[0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
}
clang does not like that behavior unless we specify
the option -Wno-initializer-overrides.
Remove the check for gcc in those places, too, because
1) it would silently change array contents between compilers
2) the check isn't sufficient to determine compilation on
clang vs gcc
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I93cc121b6fec099fcdbd5fd1114c2ff7cbc291dc
Reviewed-on: https://review.coreboot.org/20384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This requires to also unify the calling convention for
AGESA functions from
AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
to
AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr)
On systems running 32bit x86 code this will not make a difference as
UINTN is uintptr_t which is 32bit on these machines.
Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Correct all checkpatch errors but leave two errors in place
that are caused by AMD typing.
Change-Id: I9daa374da76ff991de72d16bad0e8b586aa95525
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Switch Garnenia mainboard to single soc/ directory structure.
Change-Id: I095804d603bcccf324d3244965081a9dccba62ae
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Changes the offsets of some options so that options that span multiple
bytes are byte aligned.
To make the cmos.layout file more consistent some things where moved
around in the cmos.layout of thinkpads X200 and T400.
Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: I1ef1323dc1f3005ed194ad82b75c87ef41864217
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19367
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This needs some extra headers in amdk8/raminit.c that were otherwise
provided by that file.
Change-Id: I80450e5eb32eb502b3d777c56790db90491fc995
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19360
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
For this debug.c needs to be linked too.
Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19030
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
The silicon specific mainboard_romstage_entry() in amd/cpu/car.h,
which is used by all AMD silicon car code, caused a conflict.
Move the silicon specific defines to silicon header files. Also,
no longer include car.h in the romstage file.
Change-Id: Icfc759c4c93c8dfff76f5ef9a1a985dd704cfe94
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18769
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:
1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST
The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.
Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19333
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Delete the write to PM register 0xee. This register is not
listed in the current BKDG and S4 is not currently supported
on this APU.
NDA document #47517 "A55/.../A85X fusion Controller Hub Register
Reference Guide" provides some clues on the intent of this write.
This register has always been observed to power on with a value
of 0x08 so the write has no effect.
This should be revisited again when SMI and PSP fully implement
the support required for S3.
Change-Id: I35e6c5f7ad1de7f51b018543d2f7ce82182f11e4
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18494
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This is needed if one wants to use the header more than once.
Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19029
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Add package options to the CPU Kconfig that may be selected by the
mainboard's Kconfig file. Stoney Ridge is available in FP4 and FT4
packages and each requires a unique binaryPI image. Default to the
correct blob used by the northbridge by looking at the CPU's package.
Also modify Gardenia to select the right package.
See the Infrastructure Roadmap for FP4 (#53555) and FT4 (#55349) for
additional details for the packages.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 7b8ed7b732b7cf5503862c5edc6537d672109aec)
Change-Id: I7bb15bc4c85c5b4d3d5a6c926c4bc346a282ef27
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18989
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The term 'callout' has a specific meaning in AGESA, meaning
invoking the said function from AGESA / PI proper.
OemPostParams() does not fall into that category.
Change-Id: I0ad1cbf244501207af96e0ac415a5b80ced91052
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19141
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
The term 'callout' has a specific meaning in AGESA, meaning
invoking the said function from AGESA / PI proper.
OemPostParams() does not fall into that category.
Change-Id: I45913d93323b3813fc35b1dd1fdca3d782d4b01f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19140
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Change-Id: I074dc7d5edbe3444f841e67a5644938e23118942
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18716
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Id074f3656801d412efb9485a6e2578beb9782259
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/18994
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
We define AGESA_LEGACY as an implementation of mainboard
that has its romstage main completely under mainboard/
directory. We have learnt from other platforms this approach
has several downsides when it comes to making platform-wide
improvements.
We start by creating per-family romstage.c file, which
boards will gradually take into use by removing the
AGESA_LEGACY Kconfig option we here apply to all of them.
Change-Id: Id01931e185a023039a60af16a678de9966db8d65
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18619
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
None of the boards currently have HAVE_ACPI_RESUME and
and ACPI S3 support calls should not appear under board
directories anyways.
Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18500
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Declaration of main in cpu/amd/car.h conflicts with the
definition of main required for x86/postcar.c in main_decl.h.
Change-Id: I19507b89a1e2ecf88ca574c560d4a9e9a3756f37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18615
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
These definitions do not require AGESA.h include,
and we will eventually remove agesawrapper.h files.
Change-Id: I1b5b78409828aaf2616e177bb54a054960c3869f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18588
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I7a1574259f73a52b66d03c686ae8ab70345c36ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18586
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This file is only static defines.
Change-Id: Id50a0eba1ce240df36da9bd6b2f39a263fa613df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18585
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
Change-Id: Ib37989ee7535e59b1903537995f8383d8b04387c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18584
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
It's an attempt to consolidate the access code, even if there are still
multiple implementations in the code.
Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18265
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Also make sure that no board changes behaviour because of that by adding
a static assert.
TEST=abuild over all builds still succeeds (where it doesn't if
DIMM_SPD_SIZE isn't set to 128 bytes for boards that use the
device/dram code).
Change-Id: Iddb962b16857ee859ddcf1b52d18da9b3be56449
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18254
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
The bare ACPI MMIO address 0xFED80000 was used in multiple
AMD mainboard files as well as the SB800 native code. Reduce
duplication by using a centrally defined value for all AMD
ACPI MMIO access.
Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18032
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
|
|
Correct tabs that were intended as spaces.
Change-Id: Idcf33d829f87a866b5ed880527102918d5b93842
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17905
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
|
Make the ending comment associated with "chip ...hudson" match the
appropriate directory name.
Change-Id: I5e0d6d41a2e3f963760aad08ed6108acac5b66b3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17904
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
|
An incorrect board name was propagated over various generations of mainboards.
Correct the comments for these. Addressing the todo items will come in a
later patch.
Change-Id: I4abd028fee5087955a7b6ba8d38f99c8207d24b4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17903
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Declutter the conditional building of fchec.c. Use the CONFIG
setting directly instead of ifeq ().
Change-Id: I6d3721764e66e5615a639c1979d60ff1291b5d33
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17902
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Reduce the Bettong devices and match up the comments to the
northbridge.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from e7c38571be6406453640d671210b2074a91f162e)
Change-Id: I53adff741f5cf2bd75c37421949bd30f214f5692
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17849
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Add the region used by the A-Link to AHB configuration registers.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(squashed from 2c8dafdf44cf1a84cbc25e8aa381c04c160ee705
and 3c755f70ffa36c0fc92a1da0e3f5f877c8dc9e8b)
Change-Id: I7398452c6e70b4545e16398f3fec157f2f30293a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17848
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Add the missing two I2C controllers.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from 0be00a96b9eb40c959a422a5ca4773d2353d244d)
Change-Id: I3ea74a6c0472711102b19a7ca0209aaeeeb2d601
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17847
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Remove the unused Name field. Its previous design generates an FWTS
error and a recommendation for changing it to Serialized.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1d970f1aa16c647e56a08c83f5719041882a2fc0)
Change-Id: I27748a4f84286e80043f516564ef64350ef3fef9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17846
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Turn on LPC decoding in romstage.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 5d9dae5a1fdab1bf6c418dc7e6de28069bd342dc)
Change-Id: I937eb5c5b6c6a9f7a13ebd0bec7fcc8d789427ce
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17227
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Add ALC286 commands and update the PLATFORM_CONFIGURATION structure
with the list address.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 2dd5cd2f01cd37c9eb7dff85e20e446c7d5ab2ee)
Change-Id: I037b39a8634bf886f82ed93488f1efbf6661c93f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17226
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change the Carrizo settings used for Bettong to ones specific
to Stoney on Gardenia.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit e99b2c7e2c913413fdc83ad37c5519837a38c7fb)
Change-Id: I4376421c8c08dab9d7ff1428993eed3978e89657
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17225
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Duplicate the code from DB-FT3lc and use the correct names.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 935cbe6e8b81f11291322dba3688b0a5a0c3291c)
Change-Id: I3a3c62f09819ea02388bf70945fd0c011ad7555a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17224
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Remove a duplicated check and setting for xHCI during the
AMD_INIT_RESET callout. This is handled by the wrapper. Also
remove nearby commented code. EcChannel0 is not a member of
FCH_RESET_DATA_BLOCK.
Leave the check in AMD_INIT_ENV. Although AGESA honors what
was previously requested, additional settings depend on the
state of Usb.Xhci0Enable.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit ca862fbacbe80b1345ad6f23262a9769f05c50fd)
Change-Id: I45a5123e158cd7399d6d286999371d4a0e0fa963
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17223
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change the default configuration for the following settings:
AGPIO14: BT radio disable
AGPIO64: NFC PU
AGPIO65: NFC wake
AGPIO66: Webcam
AGPIO69: PCIe presence detect
AGPIO70: GPS sleep
AGPIO116: MUX for Power Express Eval
EGPIO119: SD power
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit d146af183b9dbbd6bd6c7b6ad1b383bf36203da4)
Change-Id: Ibbde7593f3477e30a45fd4f56f236c6e94e3725f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17222
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Remove the last bit of Bettong board_id checking from Gardenia.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit b617823d1d2860a3f6d766a40ae95e5486739a5c)
Change-Id: Ibc56dbbfa1b15b21ebadb9f6c9c54936566a2986
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17221
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Gardenia doesn't have the ability to modify settings depending on
the board ID.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 536b4c424e5259ddbd82469f5f426d3189ff3f89)
Change-Id: I2c928431306c669735cf735042855e95721bb107
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17220
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Gardenia makes no special considerations for a board_id regarding
SPD access and addressing. Remove this from the source and use
the standard AGESA call.
Make SPD address changes to devicetree.cb. Note that Gardenia is
designed to be a two channel, single DIMM/channel system (some SKUs
with two DIMMs on the second channel). However, this port is for
the Stoney processor which is a single channel. As a result, the
second DIMM slot is not usable. A future improvement could involve
a port using a different processor, with unique devicetree files
for each.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 77511f98f819dfe08c3ed16ebc11e1b328bdca15)
Change-Id: Id00c2be83340ceeec043ec86e96779e6bf46ae7b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17219
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Use bettong as the reference for the gardenia mainboard.
Update makefiles etc so it builds.
This patch intentionlly keeps the carrizo_fch.asl file to
remain synchronized with the AMD PI package.
Remove items that do not apply to the Stoney APU, rewrite the
comments associated with the PCIe devices, and fix up the
SPD register association to match the 00670F00 chip.h.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit 82accfcf9ec76a042156fb6e528f7900987b6e7e)
Change-Id: I014fec5c99c01fc02e129be514b704c8ba27d464
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17218
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Id404bdab1f2361f1e7d20f7ee72111971863dddf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17736
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17735
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
These headers & comments indicating a lack of functionality don't help
anything. We discourage copyrights and licenses on empty files, so
just clear these.
Change-Id: Id2ab060a2726cac6ab047d49a6e6b153f52ffe6d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17657
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Vendorcode always does PCI MMCONF access once it is
enabled via MSR.
In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.
Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17534
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Vendorcode always does PCI MMCONF access once it is
enabled via MSR.
In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.
Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17533
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
