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2014-01-19board-status: Add board_info.txt extracted from wiki.Vladimir Serbinenko
board_info.txt is a file to be used by board-status to add some useful info to the generated table like flash chip type. This series is autogenerated from wiki page Supported_Motherboards. Change-Id: Ie2bda900713ef4883134477163320936c84c34f5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4701 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-15Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki
This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be set with values that are not power of 2. The region programmed as WB cacheable will include all of ROM_SIZE. Side-effects to consider: Memory region below flash may be tagged WRPROT cacheable. As an example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB. Since this can overlap CAR, we add an explicit test and fail on compile should this happen. To work around this problem, one needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and define a smaller region for WB cache. With this change flash regions outside CBFS are also tagged WRPROT cacheable. This covers IFD and ME and sections ChromeOS may use. Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4625 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2013-12-30AMD K8 (rev F): Move rev F0/F1 workaround to headerKyösti Mälkki
Place this in header so it works also when raminit_f.c and raminit_f_dqs.c are not #included in romstage.c build. The workaround remains to be disabled for all boards. Change-Id: Iff0271ceb21ee1e28a1a31d6bbdb97e29d76461e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4568 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridgeKyösti Mälkki
Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all K8 rev F boards do the same things here. Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4567 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-29AMD K8 (rev-F): Always have RAMINIT_SYSINFOKyösti Mälkki
K8 Rev F raminit code cannot be built without RAMINIT_SYSINFO, so have the option enabled together with K8_REV_F_SUPPORT. Also move the option under AMD K8. Change-Id: I91fa0b4ae7e3e54fbcb4a4f91eb043956cd0fb60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4582 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29AMD fam10: Drop RAMINIT_SYSINFOKyösti Mälkki
AMD fam10 raminit cannot be built without RAMINIT_SYSINFO, this is not a true option but copy-paste remainder from AMD K8. Change-Id: Id8edc112f3bacebd1732304ac9ee6e77cc6263b7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-26AMD AGESA: Drop MEM_TRAIN_SEQKyösti Mälkki
This config was for AMD K8 only. Change-Id: Ic1ce60041fef6ddee2dae0e3559fb78f088740af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4556 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-26AMD fam10: Drop MEM_TRAIN_SEQKyösti Mälkki
This config was for AMD K8 only. Change-Id: I76276405b676d1dd4d5dbf8c5b94194a670ccb25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4555 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-26AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includesKyösti Mälkki
Change-Id: Ib3a69e3364418426438f88ba14e5cf744e2414fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4524 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-26AMD boards (non-AGESA): Cleanup earlymtrr.c includesKyösti Mälkki
Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4523 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-24Remove PCI_ROM_RUN optionVladimir Serbinenko
The main purpose of option rom is to supply int* handlers. But supplying those is outside of coreboot scope and if someone needs those they should run SeaBIOS anyway which runs the option roms wonderfully. Running VGA oprom is kept because they're needed to init graphics. This patch still keeps the options to include the option roms to make them available to SeaBIOS. Change-Id: I646334cf88094d3bf8f527779a68a07e0b4b93ec Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4545 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2013-12-09AMD boards: Fix includes for microcode updatesKyösti Mälkki
No ROMCC involved, no need to include .c files in romstage.c. Change-Id: I8a2aaf84276f2931d0a0557ba29e359fa06e2fba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4501 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-07Correct file permissions.Idwer Vollering
Some files have incorrect/odd permissions, correct them: remove unnecessary +x flags. Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4490 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-05AMD Kabini: fix issue 'S3 fails to suspend after wake up from USB keyboard'Zheng Bao
Propagated from http://review.coreboot.org/3347 http://review.coreboot.org/3374 The cause of this issue is: USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event, but this bit is not clear after wake up. So OS thinks there is a wake up signal and wake up immediately. Both amd/olivehill and asrock/imb-a180 have been validated. Change-Id: I7c26cb07bcd2e62bb792809b67314e5155c6adf6 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/4261 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-05AMD Kabini: Add ACPI sleep/wakeup calls for southbridgeZheng Bao
The AML code of PTS and WAK for southbridge are in UINT8 AlibSsdtKB[], Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h. It was integrated into SSDT even it was called by nobody. The source ASL was provided by AGESA for reference, but it has been scrubbed when it was ported to Coreboot. Without the calls, Olive Hill can not wake up if it boots Windows. Both amd/olivehill and asrock/imb-a180 have been validated. Change-Id: Ia7bba29904dbd6f33fdb08bf88bb499005ef561b Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/4260 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24amd/olivehill: Fix the double spaces in copyright headerZheng Bao
Change-Id: I1bdc52efc827c331c53b97d2b96edafc518d05bf Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/4259 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-11-22AMD f15tn, f16kb: Remove CDIT table and DMI tableWANG Siyuan
On AMD Trinity and Kabini boards errors similar to the following are shown. ASSERTION FAILED: file 'src/mainboard/asrock/imb-a180/agesawrapper.c',line 431 DmiTable:100123f7, AcpiPstatein: 10010129,AcpiSrat:0,AcpiSlit:0, Mce:10010de9,Cmc:10010eab,Alib:1002111c, AcpiIvrs:0 in agesawrapper_amdinitlate agesawrapper_amdinitlate failed: 5 The reason is that on f16kb boards, the CDIT and DMI table are not created. On f15tn boards, only the DMI table is not created. Until the root cause is found, disable the table generation to remove the errors. Thanks to Wei Hu for debugging and reporting this issue on the list [1]. [1] http://www.coreboot.org/pipermail/coreboot/2013-November/076607.html CDIT table is not created Change-Id: I837e3c322bb5331a9b950a72397796a60642c3f3 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/4092 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-11-12AMD Hudson: Move function s3_resume_init_data to southbridgeZheng Bao
Besides the AGESA static settings, the settings in mainboard/buildOpt.c also change the final configuration. We need to make sure the settings in FchParam in resume stage are the same as they were in cold boot stage, otherwise the board can not wake up more than once. Tested on AMD/Olive Hill, AMD/Parmer and ASRock/imb-a180. (USB keyboard doesn't work when board wakes up. It is not introduced by this patch. It needs more debugging.) Change-Id: I5a5e5502080e358ffc3577dc6a40bb762844d998 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/3932 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2013-10-18get_bus_conf.c: reindent with indentPaul Menzel
Change-Id: Ia0c37339aa69b92a1b518fa5e49adc4a7628ae5d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3979 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-10-15AMD Olive Hill: Disable NoSnoopEnable to fix HDMI audio corruptions with UbuntuWANG Siyuan
Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can resolve this issue. I have tested on Ubuntu 13.04 with AMD Catalyst 13.4 Proprietary Linux Display Driver[1]. [1]. http://support.amd.com/us/gpudownload/linux/Pages/radeon_linux.aspx Change-Id: I5d2dddb1b7469d56cd64e3c1e0f4c6c6f095b4ab Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3934 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-10-15AMD Olive Hill: fix Windows 7 HDMI audio issueWANG Siyuan
Windows 7 cannot find HDMI audio device because of acpi setting. I have tested on Windows 7. I can play music. Change-Id: I90ade7e7be79f65783922333c2cbb2d3cc6557ea Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3933 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-10-07AMD hudson yangtze: Fix corruption of a global ramstage variableKyösti Mälkki
A late for loop may reference over the current array allocation and corrupt an unrelated global variable. As a quick fix bumb the size of the array allocation uniformly to 6. We missed these boards for commit 9c7d73ca because the arrays had been renamed. Change-Id: Iff2f2a0090d9302576bc72195d2a3f6fa37ce29a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3954 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-09-24southbridge/cimx/sb900: Rename headers to match sb700 & sb800Corey Osgood
Northbridge code includes these headers, so they all need to have the same name to allow different combinations of northbridge and southbridge. This changes the sb900 names to match sb700 & sb800, and points agesa/family12 and amd/torpedo to the new file names. Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Reviewed-on: http://review.coreboot.org/3825 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-09-17Fix whitespace leaked into treeKyösti Mälkki
Clean whitespace errors that have gotten past lint-stable-003-whitespace and gerrit review. Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3920 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-11AMD sb800 sb900: Fix corruption of a global ramstage variableKyösti Mälkki
A late for loop may reference over the current array allocation and corrupt an unrelated global variable. As a quick fix bumb the size of the array allocation uniformly to 6. Change-Id: Ib067fdf077e091d13e32cc3a8e4a0b713d19bcc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3914 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-08-16Correct spelling of shadow, setting and memoryPaul Menzel
Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3768 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15Include boot_cpu.c for romstage buildsKyösti Mälkki
ROMCC boards were left unmodified. Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15AMD Fam15tn boards: BiosCallOuts.c: Remove board name from `CodecTableList`Paul Menzel
The board name in that variable name is not necessary, as it is not board dependent, that means using the file as a template for making a new coreboot port for another motherboard the variable does not need to be changed, and just increases the code differences between AMD Parmer, AMD Thather and ASUS F2A85-M. So use a generic name. The same was done for AMD Persimmon (and inherited by the LiPPERT FrontRunner/Toucan-AF) in the following commit. commit 5e70766f14253f53190ddd49a544460c6bc1e528 Author: Jens Rottmann <JRottmann@LiPPERTembedded.de> Date: Tue Feb 26 15:56:11 2013 +0100 AMD Fam14 boards: reduce unnecessary differences, 2nd attempt Reviewed-on: http://review.coreboot.org/2529 The board name is *not* removed from the `CODEC_ENTRY` variable name as the verb table not only depends on the codec but also on the board [1]. Having the board name in the variable name is a good indicator that the pin configuration needs to be adapted when taking this file as a template for a new port. If it was board independent, a default chip configuration could be used and shared between all boards, which is unfortunately not the case. [1] Unfortunately I was not able to find Jens’ comment in my mail archive and in the Gerrit Web interface. Not sure where it is, but I am sure he made that comment. Change-Id: I440a306cf4ff0a5b1b61d1983d70c66d129904d0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3199 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15AMD Kabini: Split DSDT into common sectionsMike Loptien
Split the Family16 (Kabini) DSDT file into logical regions. Olive Hill is the only mainboard and Kabini is the only NB/CPU currently using Family16 AGESA code. Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3821 Tested-by: build bot (Jenkins)
2013-08-08AMD Thatcher: Split DSDT into common sections (as per Parmer)Kimarie Hoot
Rearranged the Thatcher DSDT file to match the functionality found on Parmer. As with the Parmer implementation, the Thatcher dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. As with Parmer, some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for Thatcher. Change-Id: Ie44a32959cc547840914365e872416d4624d33df Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/3804 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06AMD Olive Hill: Enable WARNINGS_ARE_ERRORS (remove override)Bruce Griffith
Change-Id: Idf26eb3fb541355bd9553c1897f647738c347eb5 Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/3819 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-06AMD Olive Hill: Change SB800 references to YangtzeBruce Griffith
Change-Id: I7f6f6ff444fda4bdf233db1383919772afe6b635 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3815 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06AMD Olive Hill: Add HUDSON_LEGACY_FREE flagBruce Griffith
Olive Hill does not have a Super I/O or keyboard controller. Change-Id: I8c1e5d8c20c4a964fe8d98df920b416382a26d9d Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3848 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06AMD Olive Hill: Remove default VBIOS vendor/device IDBruce Griffith
The VBIOS device ID is set by processor family using the map_oprom_vendev() function in the northbridge code. There is rarely a reason why this should be overridden by the mainboard. Since Kabini includes a default VBIOS vendor/device ID in the northbridge Kconfig code, remove the setting from the Olive Hill mainboard settings. Change-Id: Icd69155f5b51105d564dd82c89e4bb54a6118a82 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3816 Tested-by: build bot (Jenkins)
2013-08-05AMD Olive Hill: Enable HDMI audio setting in build optionsBruce Griffith
Change-Id: Ifc180e6fcd594dbedc2512ea5bef283a3ad689d3 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3814 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05AMD Olive Hill: Eliminate unnecessary memory copyBruce Griffith
Eliminate an unnecessary copy of the DDI descriptor list and the PCIe port descriptor list. As descriptor tables, these tables do not need dynamic updating and should be used from ROM without runtime copying. There will be a corresponding patch for AGESA that adds CONST modifiers to function parameters that are pass-by-reference "IN" values (read-only pointers). Change-Id: I7ab78e58041e9247db22d0f97a6f76d45f338db0 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/3818 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05AMD Olive Hill: Add new AMD mainboard using Kabini processorSiyuan Wang
Change-Id: I1f252b67c039d28df96e8dfd458a1ca6a7dbc816 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3784 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-07-26AMD Parmer: Fix file permissions on asl files in mainboardKimarie Hoot
Removed the execute bit on all files in mainboard/amd/parmer/acpi Change-Id: I85ffa66e0beb9c4bfe826b72968f7f633c224487 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/3807 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-16AMD Fam15tn: Split DSDT into common sectionsSteve Goodrich
Split the Parmer, Family 15tn, and Hudson DSDT into groups. This splits the DSDT table into includable ASL files which carry details specific to the Family 15tn APU, the Parmer platform, and the Hudson FCH. The dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. Initially, this split was done by moving each piece of functionality into its own file (e.g. IRQ routing and mapping, processor tree, sleep states and sleep methods, etc.) and those pieces were #included in dsdt.asl to ensure an exact match (via acpidump/acpixtract/iasl -d) with the extant version of the table. Once the new tables were found to exactly match the existing tables, the pieces were rearranged into reasonable groups (e.g. fch.asl, northbridge.asl, pci_int.asl, etc.). Some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for Parmer (e.g. thermal.asl, superio.asl, ide.asl, sata.asl, etc.). Change-Id: I098b0c5ca27629da9bc1cff1e6ba9fa6703e2710 Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com> Reviewed-on: http://review.coreboot.org/3629 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-07-10Rename hardwaremain() to main()Stefan Reinauer
... and drop the wrapper on ARMv7 Change-Id: If3ffe953cee9e61d4dcbb38f4e5e2ca74b628ccc Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3639 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28Drop WARNINGS_ARE_ERRORS exceptionsStefan Reinauer
Thanks to Bruce's great work, we can finally drop this workaround. Change-Id: Ie92d1e53ef867fa34aa2489ccfb682d73195b213 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3569 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-28AMD Dinar: Eliminate warnings (initializers/prototypes/unused var)Bruce Griffith
Fix a bunch of compiler-generated warning messages. These fixes are mainly braces for grouping initializers. These changes are not intended to change any code functionality. There are two changes where function prototypes are added, and two cases where unused variables are eliminated. Change-Id: I93cef8899170b5575e7fb7c55181b381a7bcd9d8 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3545 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28AMD SB700 boards: Set Azalia configuration flagsBruce Griffith
The existing code for setting Azalia configuration assumes that the configuration bits are contiguous within a single byte and can be set using a byte copy addressed into the lowest 2-bit subfield. The fix in Family 14 defines a union that can be addressed as a byte to overlay the bit fields. Since the offset of the four subfields is not necessarily fixed, change the code to initialize each of the four subfields individually. Change-Id: I1dff20bb8bd3e1bcd8b4e6b0537e20779d2a3521 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3544 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28Dinar, H8SCM, H8QGI: Add prototype of get_bus_conf()Bruce Griffith
On Dinar, H8SCM, and H8QGI, add <cpu/amd/amdfam15.h> as an include to pick up the prototype definition of get_bus_conf(). Change-Id: Ie4887670ac52aa194745881362df19cd1d75773e Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3542 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-24AMD: Drop empty root_complexKyösti Mälkki
There are no files to build left under AMD nortbridge/x/root_complex directories. For some cases, even the Kconfig file was no longer sourced. Remove all such references and empty files. For devicetree.cb treat component paths with "/root_complex" in them valid even when the directory does not exists. This is because AMD boards us this dummy chip component as the root node in their devicetree.cb. The generated devicetree file static.c remains unchanged. Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3434 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-23AMD boards: routing.asl: Uniformly start `Package()` with capital letterPaul Menzel
In commit Rudolf Marek discovered, that it is not uniformly written. As »ASL names are not case-sensitive and will be converted to upper case.« [2] this change does not have any functional change. The following command was used to create this patch. $ git grep -l 'package()' src/mainboard | xargs sed -i 's,package(),Package(),' [1] http://review.coreboot.org/#/c/3318/ [2] http://www.acpi.info/spec40a.htm (18.2.1 ASL Names) Change-Id: I1784dbc50936a1ef9d4376209a3c324ef1fb85cf Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3516 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17AMD southbridges: Move HAVE_HARD_RESETKyösti Mälkki
All 3 boards with AGESA_HUDSON had HAVE_HARD_RESET with the reset.c file already placed under southbridge/. All 15 boards with CIMX_SBx00 had HAVE_HARD_RESET with functionally identical reset.c file under mainboard/. Move those files under respective southbridge/. Change-Id: Icfda51527ee62e578067a7fc9dcf60bc9860b269 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3486 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17AMD boards: Clean use of Kconfig optionsKyösti Mälkki
The chip component is unconditionally selected for the mainboard so these uses are superfluous. Change-Id: I84b053ab47f7b1f68e88d968cf305e24bc95f4da Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3485 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17Add support for XHCI (USB 3.0)Dave Frodin
CONFIG_HUDSON_XHCI_ENABLE will control the XHCI flags in the amd/parmer and asus/f2a85-m mainboards. The XHCI ports on amd/thatcher are not wired to USB jacks so always disable the flags. This was tested on amd/parmer using a USB 3.0 thumbdrive. Change-Id: I596b040fec30882d8d4dee34ab9f866dc1f8896b Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/3465 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13AMD Thatcher: fix issue 'S3 fails to suspend after wake up from USB keyboard'Siyuan Wang
This issue can be reproduced in Linux by the following steps: 1) use pm-suspend to suspend. 2) use USB keyboard to wake up. 3) use pm-suspend to suspend. FAIL To SUSPEND. The cause of this issue is: USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event, but this bit is not clear after wake up. So OS thinks there is a wake up signal and wake up immediately. In this patch, I add AcpiGpe0Blk using MMIO access and write 1 on bit 11. Write 1 to clear as spec says. I have tested on Thatcher The same change was done for AMD Parmer in commit »AMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard' (03901124) [1]. [1] http://review.coreboot.org/#/c/3347/ (Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1) Change-Id: Iaef39237497ef896d0f186e8f5522222c0ce6cb7 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3374 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06AMD Trinity: Remove unnecessary lookup table copyBruce Griffith
The DDI connector table and the PCIe Port List lookup table are copied onto HEAP. This copy is not needed since these are lookup tables used to define the platform configuration. Change-Id: If4760f80e08faa8da4fd11337a3812f89cf805f9 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c"Christian Gmeiner
Change-Id: I249c63646267ebe8dd8e06980aa6367a16fe7297 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3370 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: convert spd_read_byte() to non-static versionChristian Gmeiner
Change-Id: Ie329606852dfd7109acb694e9a9ff851b023cc63 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3369 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: move #include "northbridge/amd/lx/raminit.h"Christian Gmeiner
Move the include before static inline int spd_read_byte(). Change-Id: I4cac4b1f55368041b067422d95c09208e15d0f2d Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3368 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-31AMD Trinity boards: Add reserved memory area for SPI base address in ACPISteven Sherk
- SPI controller base address gets overwritten by SD controller under Linux. - Reason for overwrite is the SPI base address isn't in a standard BAR and doesn't get automatically reserved. Solution is to add it as a reserved memory area in ACPI. - This issue was found on the ASUS F2A85-M platform. Currently a workaround on this platform was made as part of: http://review.coreboot.org/#/c/3167/3 - Once approved a follow-on patch for other southbridges using a non-standard BAR for the spi controller. Change-Id: I1b67da3045729a6754e245141cd83c5b3cc9009e Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/3270 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-31AMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard'Siyuan Wang
This issue can be reproduced in Linux by the following steps: 1) use pm-suspend to suspend. 2) use USB keyboard to wake up. 3) use pm-suspend to suspend. FAIL To SUSPEND. The cause of this issue is: USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event, but this bit is not clear after wake up. So OS thinks there is a wake up signal and wake up immediately. In this patch, I add AcpiGpe0Blk using MMIO access and write 1 on bit 11. I have tested on Parmer. Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3347 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-30AMD Llano, Brazos boards: Use `sizeof(var)` to get its sizePaul Menzel
Change `sizeof(type) * n`, where n is the number of array elements, to `sizeof(variable)` to directly get the size of the variable (struct, array). Determining the size by counting array elements is error prone and unnecessary. Rudolf Marek’s patch »ASUS F2A85-M: Correct and clean up PCIe config« [1] contains the same change and is ported over. In the commit message Rudolf makes the following comment. »Not sure why the copy is needed instead of direct reference. Maybe it has something to do with CAR?« Testing on the ASRock E350M1, no regressions were noticed. [1] http://review.coreboot.org/#/c/3194/ Change-Id: I123031b3819a10c9c85577fdca96c70d9c992e87 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3248 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-30AMD Trinity boards: Use `sizeof(var)` to get its sizeRudolf Marek
Change `sizeof(type) * n`, where n is the number of array elements, to `sizeof(variable)` to directly get the size of the variable (struct, array). Determining the size by counting array elements is error prone and unnecessary. Not sure why the copy is needed instead of direct reference. Maybe it has something to do with CAR? These changes are based on Rudolf’s original patch »ASUS F2A85-M: Correct and clean up PCIe config« [1], where it was just done for the ASUS board. [1] http://review.coreboot.org/#/c/3194/ Change-Id: I4aa4c6cde5a27b7f335a71afc21d1603f2ae814b Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3247 Tested-by: build bot (Jenkins) Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-17AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for bufferBruce Griffith
The following commit commit 05f3b117dd44776ed17bc57318f260766039b7e8 Author: Paul Menzel <paulepanter@users.sourceforge.net> Date: Tue May 14 09:28:26 2013 +0200 AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer Reviewed-on: http://review.coreboot.org/3246 changed one calculation for the size of the array PortList[] to reflect only four elements, but neglected three additional calculations of the size of the same table. Correct that by setting the size for four array elements in all four calculations. [1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbPcie.c Change-Id: Ib66b7b2b388d847888663e9eb6d1c8c9d50b9939 Reported-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3250 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-05-16AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for bufferPaul Menzel
The following commit commit d0790694b0a66353e5531715648ddaa1a6d577cb Author: Kerry Sheh <shekairui@gmail.com> Date: Thu Jan 19 13:18:37 2012 +0800 Inagua: Inagua GNB ddi lanes and pcie lanes config update Reviewed-on: http://review.coreboot.org/544 assigns lanes 4 and 5 to PCI device number 4, but does not adapt the rest of the code. After the commit above, the array `PortList []` only has four elements, but the buffer size `AllocHeapParams.RequestedBufferSize` is set to a size as it still has five elements. Correct that by setting the size for four array elements. [1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbPcie.c Change-Id: I3ff07f308ffd417d2bf73117eda9da2a1a05f199 Reported-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3246 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-14AMD Fam15tn boards: BiosCallOuts.c: Declare codec arrays as `static`Paul Menzel
These arrays are declared as `static` for AMD SB800 based boards, so do the same for this generation. Rudolf Marek just changed `const CODEC_TBL_LIST` to `static const` in [1]. Adapt all Fam15tn based boards (AMD Parmer, AMD Thatcher, ASUS F2A85-M) to keep the differences between them small. [1] http://review.coreboot.org/#/c/3170/3/src/mainboard/asus/f2a85-m/BiosCallOuts.c Change-Id: I353b38bd8bc77ba500a4b7fe9250e9aa3071c530 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3198 Tested-by: build bot (Jenkins)
2013-05-14AMD Fam15tn boards: Document lane ID mapping from BKDGRudolf Marek
To make it easier to fill in the values, place the table from the BIOS and Kernel Developer’s Guide (BKDG) [1] as a comment. [1] http://www.coreboot.org/Datasheets#AMD_Fam15 Change-Id: I218f76e9fa2dc88d47af51ea6c062e315afb0000 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3221 Tested-by: build bot (Jenkins)
2013-05-14AMD Brazos/Trinity boards: PlatformGnbPcie.c: Reserve correct amount of memoryPaul Menzel
In `PlatformGnbPcie.c` AGESA functions are used to reserve memory space to save the PCIe configuration to. This is the With the following definitions in `AGESA.h` $ more src/vendorcode/amd/agesa/f14/AGESA.h […] /// PCIe port descriptor typedef struct { IN UINT32 Flags; /**< Descriptor flags * @li @b Bit31 - last descriptor in complex */ IN PCIe_ENGINE_DATA EngineData; ///< Engine data IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info } PCIe_PORT_DESCRIPTOR; /// DDI descriptor typedef struct { IN UINT32 Flags; /**< Descriptor flags * @li @b Bit31 - last descriptor in complex */ IN PCIe_ENGINE_DATA EngineData; ///< Engine data IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info } PCIe_DDI_DESCRIPTOR; /// PCIe Complex descriptor typedef struct { IN UINT32 Flags; /**< Descriptor flags * @li @b Bit31 - last descriptor in topology */ IN UINT32 SocketId; ///< Socket Id IN PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). IN PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). IN VOID *Reserved; ///< Reserved for future use } PCIe_COMPLEX_DESCRIPTOR; […] memory has to be reserved for the `PCIe_COMPLEX_DESCRIPTOR` and, as two struct members are pointers to arrays with elements of type `PCIe_PORT_DESCRIPTOR` and `PCIe_DDI_DESCRIPTOR`, space for these times the number of array elements have to be reserved: a + b * 5 + c * 2. sizeof(PCIe_COMPLEX_DESCRIPTOR) + sizeof(PCIe_PORT_DESCRIPTOR) * 5 + sizeof(PCIe_DDI_DESCRIPTOR) * 2; But for whatever reason parentheses were put in there making this calculation incorrect and reserving too much memory. (a + b * 5 + c) * 2 So, remove the parentheses to reserve the exact amount of memory needed. The ASRock E350M1 still boots with these changes. No changes were observed as expected. Rudolf Marek made this change as part of his patch »ASUS F2A85-M: Correct and clean up PCIe config« [1]. Factor this hunk out as it affects all AMD Brazos and Trinity based boards. [1] http://review.coreboot.org/#/c/3194/ Change-Id: I32e8c8a3dfc5e87eb119eb17719d612e57e0817a Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3239 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-10AMD Thatcher: remove unused macros in PlatformGnbPcieComplex.hSiyuan Wang
The macros GNB_GPP_PORTx_PORT_PRESENT, GNB_GPP_PORTx_SPEED_MODE, GNB_GPP_PORTx_LINK_ASPM and GNB_GPP_PORTx_CHANNEL_TYPE are not used. Change-Id: I5c7b7d45880367dba452ebcd4f01fbd0c15aac22 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3087 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-09AMD: Reduce stack size from 64 KB to the default of 4 KBPaul Menzel
Apply the following commit to all AMD boards. commit 935850e08293cec1cb27d12358b27285e780566a Author: Stefan Reinauer <reinauer@chromium.org> Date: Mon May 6 16:16:03 2013 -0700 asrock/e350m1: reduce default stack size The stack used on the ASRock E350M1 is significantly less than what we currently set (64k per core). In fact, we use about half of the default stack size (4k) on core 0 and even less on non BSP cores [1]: $ grep stack coreboot_without_patch_but_monotonic_timer.log CPU1: stack_base 002a0000, stack_end 002afff8 CPU1: stack: 002a0000 - 002b0000, lowest used address 002afda8, stack used: 600 bytes CPU0: stack: 002b0000 - 002c0000, lowest used address 002bf75c, stack used: 2212 bytes […] Reviewed-on: http://review.coreboot.org/3209 Please note that AGESA seems to define bigger stack sizes. But these seem to be too much too. $ git grep STACK_SIZE src/vendorcode/amd […] src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define BSP_STACK_SIZE 16384 src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define CORE0_STACK_SIZE 16384 src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define CORE1_STACK_SIZE 4096 src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c: BSP_STACK_SIZE, src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c: CORE0_STACK_SIZE, src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c: CORE1_STACK_SIZE, […] The following command was used to create the patch. $ git grep -l STACK_SIZE src/mainboard/ | xargs sed -i '/STACK_SIZE/,+3d' Change-Id: I36b95b7a6f190b64d0639fc036ce2fb0253f3fa1 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3217 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-08Drop CONFIG_AP_CODE_IN_CARStefan Reinauer
This option has not been enabled on any board and was considered obsolete last time it was touched. If we need the functionality, let's fix this in a generic way instead of a K8 specific way. This was mostly a speedup hack back in the day. Change-Id: Ib1ca248c56a7f6e9d0c986c35d131d5f444de0d8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3211 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-08copy_and_run: drop boot_complete parameterStefan Reinauer
Since this parameter is not used anymore, drop it from all calls to copy_and_run() Change-Id: Ifba25aff4b448c1511e26313fe35007335aa7f7a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3213 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-03mainboard/{asus/f2a85-m,amd/thatcher}: move UDELAY_LAPICDavid Hubbard
Stefan Reinauer suggested 'select UDELAY_LAPIC' did not belong in f2a85-m/Kconfig. It got there via copy-paste from thatcher/Kconfig so this commit removes the 'select UDELAY_LAPIC' from both and puts it in cpu/amd/agesa/family15tn/Kconfig Since f2a85-m is the only Thatcher board coreboot supports right now, this should not break any other boards. Change-Id: I811b579c31f8d259a237d3a6724ad3b17f3a6c3e Signed-off-by: David Hubbard <david.c.hubbard+coreboot@gmail.com> Reviewed-on: http://review.coreboot.org/3178 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2013-05-01AMD Hudson A55E: Remove GEC firmware blob kconfig promptBruce Griffith
The "gigabit ethernet controller" (GEC) block was added to AMD Hudson A55E to integrate ethernet capabilities into an AMD southbridge. The GEC is designed to work with B50610 and B50610M gigabit PHY chips from Broadcom. These parts may not be generally available in small quantities for embedded development. The GEC block requires an opaque firmware blob to function. The GEC blob is controlled by AMD and Broadcom and is not available from coreboot.org. This change removes GEC support from AMD Parmer and AMD Thatcher mainboards since these boards do not have the Broadcom PHY. AMD has requested that the GEC be hidden for Hudson FCH since the PHY parts are not generally available. This Kconfig option can make it appear that this is a viable and supported way to add Ethernet to an embedded board. It is possible to use the Hudson GEC block with other PHYs, but this requires development of a custom GEC blob and a custom Ethernet driver. A custom GEC blob has been developed for a Micrel PHY, but there is no accompanying driver. Change-Id: I7a7bf4d41e453390ecf987c9c45ef2434fc1f1a3 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3127 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-23AMD Thatcher: ConnectorTypeDP supports both DP and HDMISiyuan Wang
It seems that ConnectorTypeDP in DdiList supports both DP and HDMI monitors. I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter. Video and audio are OK. Hot plugging is also supported. This commit partially reverts commit >AMD Thatcher: Fix PCIE link issues< (7f23aeb0) [1]. [1] http://review.coreboot.org/3011 Change-Id: I23cf1c69a8274f47daf56f1a12aafd88bad4a128 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3088 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-20AMD SB800 based boards: Use `#include <sb_cimx.h>` instead of `"sb_cimx.h"`Paul Menzel
Due to $ more src/southbridge/amd/cimx/sb800/Makefile.inc […] romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c ramstage-y += cfg.c ramstage-y += late.c […] `src/southbridge/amd/cimx/sb800/` is passed with the switch `-I` to the compiler, where it is also going to find the header file `sb_cimx.h`. Therefore use `#include <sb_cimx>` everywhere, which is what some AMD SB800 based boards already do. The only effect is, that the compiler will not needlessly look into directories which do not contain the header file [1]. The following command was used for the replacement. $ git grep -l sb_cimx.h src/mainboard/ | xargs sed -i 's/#include "sb_cimx.h"/#include <sb_cimx.h>/' [1] http://gcc.gnu.org/onlinedocs/cpp/Search-Path.html Change-Id: I96ab34bac1524e6c38c85dfe9d99cb6ef55e6d7c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3118 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19AMD Parmer: change DdiList to ConnectorTypeDP to support DP and HDMISiyuan Wang
This patch is based on >>AMD Thatcher: ConnectorTypeDP supports both DP and HDMI<< (I23cf1c6) [1] I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter. Video and audio are OK. Hot plugging is also supported. [1] http://review.coreboot.org/#/c/3088/ Change-Id: I291beff43609ecb68ece24939f2dbc7c08dd0374 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3090 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18AMD Fam14: Split out the AMD Fam14 DSDTMike Loptien
Same splitting as done on Persimmon and ASRock. Moving common DSDT code to common areas and adding new files as necessary. Boards updated are: Inagua Union-Station South-Station Change-Id: I8c9eea62996b41cea23a9c16858c4249197f6216 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3051 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16AMD Parmer: remove unused macros and turn off unused pcie portSiyuan Wang
1) The macros GNB_GPP_PORTx_PORT_PRESENT, GNB_GPP_PORTx_SPEED_MODE, GNB_GPP_PORTx_LINK_ASPM and GNB_GPP_PORTx_CHANNEL_TYPE are not used. This is based on >AMD Thatcher: remove unused macros in PlatformGnbPcieComplex.h< [1]. 2) Disable unused PCIE port in devicetree.cb. PCIE port 3 is not used in Parmer. This is based on item 3 of >AMD Thatcher: Fix PCIE link issues< [2]. [1] http://review.coreboot.org/#/c/3087/ [2] http://review.coreboot.org/#/c/3011/ Change-Id: Id6f00d5e77ce5133d9ef3db07f95ad03a59e061a Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3099 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-12AMD Thatcher: Fix PCIE link issuesSiyuan Wang
1). Thatcher PCIE x8 slot is reverse order. Although the PCIE slot is x16, it actually uses 8 lanes(15:8). Because the PCIE slot is configured by PortList[0], fix this item can enable the slot. A x1 PCIE network adapter works well in this slot. 2). Fix DdiList to detect DP monitor or HDMI monitor. GPIO50 can be used to detect DP0/HDMI0 monitor. If GPIO50 is 1, it is DP monitor. If GPIO50 is 0, it is HDMI monitor. GPIO51 can be used to detect DP1/HDMI1 in the same way. 3). Disable unused PCIE port and clean up code in PlatformGnbPcie.c and devicetree.cb. PCIE port 3 and 7 are not used in Thatcher. Change-Id: I8524b6fc1b6cdc03ba92e7191186bfb0986767c8 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3011 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-11Persimmon/Fam14/SB800 DSDT: Split into common areasMike Loptien
Split the Persimmon DSDT into common code areas. For example, split the Southbridge specific code into the Southbridge directory and CPU specific code into the CPU directory. Also adding the superio.asl file to the Persimmon DSDT tree. This file is empty for the moment but will be necessary in the future. I have also emptied the thermal.asl file in the mainboard directory because it does not seem to perform as intended (fan control does not change when it is brought back into the code base) and it has been inside a '#if 0' statement for a long time. Removing it until it is decided that it is actually necessary. This change was verified in three different ways: 1. Visual comparison of the compiled DSDT pulled from the Persimmon after booting into Linux using the ACPI tools acpidump, acpixtract, and iasl. The comparison was done between the DSDT before and after doing the split work. This test is somewhat difficult considering the expanse of the changes. Blocks of code have been moved, and others changed. 2. Linux logs were dumped before and after the DSDT split. Logs dumped and compared include dmesg and lspci -tv. Neither log changed significantly between the two compare points. 3. The test suite FWTS was run on the Coreboot build both before and after doing the DSDT split with the command 'sudo fwts -b -P -u'. The flag -b specifies all batch jobs, -P specifies all power tests, and -u specifies utilities. Interactive jobs were not run as most of them consist of laptop checks. Again, there were no significant changes between the two endpoints. These tests lead me to believe that there was no change in the functionality of the ACPI tables apart from what is known and expected. This patch is the first of a series of patches to split the DSDT. The ASRock patch was merged before this one and breaks the ASROCK E350M1 build (patch 8d80a3fb: http://review.coreboot.org/#/c/3050/). Please be aware of this dependency when pulling these patches. Other patches that depend on this patch are 'AMD Fam14: Split out the AMD Fam14 DSDT' (http://review.coreboot.org/#/c/3051/) and 'Fam14 DSDT: Also return for unrecognized UUID in _OSC' (http://review.coreboot.org/#/c/3052/) Change-Id: I53ff59909cceb30a08e8eab3d59b30b97c802726 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3048 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-03Partially revert "AMD Inagua: broadcom.c: Add missing prototype for ↵Jens Rottmann
`broadcom_init()`" Commit 5d741567 added a prototype to broadcom.c to fix a warning. This part is fine. It also changed mainboard.c to #include broadcom.c. But broadcom.c is already in Makefile.inc, now building will fail because the linker gets broadcom_init() twice. Undo the change to mainboard.c but keep the change to broadcom.c. Change-Id: Ieccc098f477ffacccf4174056998034a220a9744 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/3012 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-30AMD Hudson boards: Use `hudson.h` for `pm_ioread` and delete `pmio.h`Paul Menzel
Unfortunately, an unneeded mainboard specific `pmio.h` was created when merging the AMD Parmer and Thatcher ports. Rudolf used the header from a more generic location southbridge/amd/agesa/hudson/hudson.h doing the the ASUS F2A85-M port, but did not delete the `pmio.h` now unused `pmio.h` header file. So adapt AMD Parmer and Thatcher to use the Hudson one as done for the ASUS F2A85-M and delete the now unused mainboard specific header file `pmio.h` to avoid duplication. Change-Id: I961cd145ebc3b83e31c638ac453ac95ee19c18db Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2958 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-29AMD Inagua: Kconfig: Remove `WARNINGS_ARE_ERRORS` to treat warnings as errorsPaul Menzel
Now that the AMD Inagua builds without any warnigs, remove the config option `WARNINGS_ARE_ERRORS` set to no by default from the file `Kconfig` so warnings are treated as errors to prevent code from being added in the future introducing warnings. Change-Id: I0b58bd74b06dc54d180b16d6a207354b5fea0d0f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2953 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29AMD Inagua: broadcom.c: Add missing prototype for `broadcom_init()`Paul Menzel
Building the AMD Inagua board, the following warning is thrown. CC mainboard/amd/inagua/get_bus_conf.ramstage.o src/mainboard/amd/inagua/broadcom.c:319:6: warning: no previous prototype for 'broadcom_init' [-Wmissing-prototypes] This warning was introduced by commit 3926b4c5. commit 3926b4c520e74da9dc22e3d136a8a178483e0d25 Author: Jens Rottmann <JRottmann@LiPPERTembedded.de> Date: Fri Mar 1 19:41:41 2013 +0100 AMD Inagua: add GEC firmware, document Broadcom BCM57xx Selfboot Patch format Reviewed-on: http://review.coreboot.org/2831 Adding the prototype to `broadcom.c` and removing it from `mainboard.c` fixes the warning. Change-Id: I1da0c4e972e129047dd8230d573f1c43fd71eb20 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2952 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-25AMD Inagua: add GEC firmware, document Broadcom BCM57xx Selfboot Patch formatJens Rottmann
The Broadcom BCM5785 GbE MAC integrated in the AMD Hudson-E1 requires a secret sauce firmware blob to work. As Broadcom wasn't willing to send us any documentation (or a firmware adapted to our Micrel PHY) I had to figure out everything by myself in many weeks of hard detective work. In the end we had to settle for a different solution, the modified firmware I devised for the Micrel KSZ9021 PHY on our early FrontRunner-AF prototypes is no longer needed for the production version. However the information contained here might be very useful for others who'd like to use a competing PHY instead of Broadcom's 50610, so it should not get lost. And of course the unmodified, but now in large parts documented Selfboot Patch is needed to get Ethernet on AMD Inagua. The code introduced here should make the Hudson's internal MAC usable without having to add the proprietary firmware blob. - At least in theory. Unfortunately we've been unable to actually test this patch on Inagua, therefore the broadcom_init() call in mainboard.c was left commented out. If you have the hardware and can confirm it works please enable it. The fun thing is: as Broadcom refused to do any business with us at all, or send us any documentation, we never had to sign an NDA with them. This leaves me free to publish everything I have found out. :-) Change-Id: I94868250591862b376049c76bd21cb7e85f82569 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2831 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-20AMD Dinar: Use SPD read code from F15 wrapperKimarie Hoot
Changes: - Get rid of the dinar mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2777/ AMD Fam15: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. - select_socket() and restore_socket() were created from code that was removed from AmdMemoryReadSPD() in dimmSpd.c. The functionality is specific to the dinar mainboard configuration and was therefore split from the generic read SPD functionality. Change-Id: I1e4b9a20dc497c15dbde6d89865bd5ee7501cdc0 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-19AMD Dinar: Remove Unused Oem.h Header FileKimarie Hoot
Having this header file in the mainboard directory breaks the dinar build on cygwin because the header file in the dinar mainboard is used instead of the correct header file src/vendorcode/amd/cimx/sb700/OEM.h. The build probably works fine on Linux systems because, due to case-sensitivity, Oem.h will not match the #include "OEM.h" statement in src/southbridge/amd/cimx/sb700/Platform.h. The Oem.h file in the dinar mainboard is not used by any other source files, and the defines in the dinar mainboard are duplicated by defines in the correct OEM.h file. Therefore, the file can be safely removed. Change-Id: I81b97eca8116d63644d335edc3bb51f90c7094d9 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2776 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-03-17AMD Fam14 DSDT: Remove INI method from AZHD deviceMike Loptien
I am removing the _INI method from the AZHD device because it does not seem to do anything and causes errors in the FWTS[1] (Firmware Test Suite) test 'method'. The INI method performs device specific initialization and is run when OSPM loads a description table. It must only access OperationRegions that have been indicated as available by the _REG (Region) method. We do not have a _REG method and during my testing, I added a REG method but it did not seem to make a difference in the PCI register space. The bit fields defined as NSDI (Disable No Snoop), NSDO (Disable No Snoop Override), and NSEN (Enable No Snoop Request) do not ever get written from their default values. And writing to these bit fields does not seem to be necessary because I did not notice any change in audio functionality. In an effort to clean up as many FWTS errors as possible, I propose removing this method altogether. I have seen no change in operation (audio works with and without this method) and there does not seem to be any change in lspci or dmesg. FWTS information can be found here: [1]: https://wiki.ubuntu.com/Kernel/Reference/fwts This is the same chagne as made to Persimmon in Change-ID If8d86f: http://review.coreboot.org/#/c/2726/ Change-Id: Id560ea85a38f73aaba2c35447bbce46bd9c0d0dd Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2741 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-17AMD Fam14 DSDT: Add OSC methodMike Loptien
The _OSC method is used to tell the OS what capabilities it can take control over from the firmware. This method is described in chapter 6.2.9 of the ACPI spec v3.0. The method takes 4 inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and returns a Capabilites Buffer the same size as the input Buffer. This Buffer is generally 3 Dwords long consisting of an Errors Dword, a Supported Capabilities Dword, and a Control Dword. The OS will request control of certain capabilities and the firmware must grant or deny control of those features. We do not want to have control over anything so let the OS control as much as it can. The _OSC method is required for PCIe devices and dmesg checks for its existence and issues an error if it is not found. This is the same change made to Persimmon with Change-ID I149428: http://review.coreboot.org/#/c/2684/ Change-Id: If6dd1a558d9c319d9a41ce63588550c8e81e595f Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2738 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-15AMD Fam14 DSDT: Add secondary bus range to PCI0Mike Loptien
Adding the 'WordBusNumber' macro to the PCI0 CRES ResourceTemplate in the Persimmon DSDT. This sets up the bus number for the PCI0 device and the secondary bus number in the CRS method. This change came in response to a 'dmesg' error which states: '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS' By adding the 'WordBusNumber' macro, ACPI can set up a valid range for the PCIe downstream busses, thereby relieving the Linux kernel from "guessing" the valid range based off _BBN or assuming [0-0xFF]. The Linux kernel code that checks this bus range is in `drivers/acpi/pci_root.c`. PCI busses can have up to 256 secondary busses connected to them via a PCI-PCI bridge. However, these busses do not have to be sequentially numbered, so leaving out a section of the range (eg. allowing [0-0x7F]) will unnecessarily restrict the downstream busses. This is the same change as made to Persimmon with change-id I44f22: http://review.coreboot.org/#/c/2592/ Change-Id: I9017a7619b3b17e0e95ad0fe46d0652499289b00 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2735 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-15Persimmon DSDT: Remove INI method from AZHD deviceMike Loptien
I am removing the _INI method from the AZHD device because it does not seem to do anything and causes errors in the FWTS[1] (Firmware Test Suite) test 'method'. The INI method performs device specific initialization and is run when OSPM loads a description table. It must only access OperationRegions that have been indicated as available by the _REG (Region) method. We do not have a _REG method and during my testing, I added a REG method but it did not seem to make a difference in the PCI register space. The bit fields defined as NSDI (Disable No Snoop), NSDO (Disable No Snoop Override), and NSEN (Enable No Snoop Request) do not ever get written from their default values. And writing to these bit fields does not seem to be necessary because I did not notice any change in audio functionality. In an effort to clean up as many FWTS errors as possible, I propose removing this method altogether. I have seen no change in operation (audio works with and without this method) and there does not seem to be any change in lspci or dmesg. FWTS information can be found here: [1]: https://wiki.ubuntu.com/Kernel/Reference/fwts Change-Id: If8d86f959822d528c44ab011a851659d486289b5 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2726 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-15Persimmon DSDT: Add OSC methodMike Loptien
The _OSC method is used to tell the OS what capabilities it can take control over from the firmware. This method is described in chapter 6.2.9 of the ACPI spec v3.0. The method takes 4 inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and returns a Capabilites Buffer the same size as the input Buffer. This Buffer is generally 3 Dwords long consisting of an Errors Dword, a Supported Capabilities Dword, and a Control Dword. The OS will request control of certain capabilities and the firmware must grant or deny control of those features. We do not want to have control over anything so let the OS control as much as it can. The _OSC method is required for PCIe devices and dmesg checks for its existence and issues an error if it is not found. Change-Id: I1494285def7440972f0549b7cb73eb94dafc72c2 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2684 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-08Persimmon DSDT: Add secondary bus range to PCI0Mike Loptien
Adding the 'WordBusNumber' macro to the PCI0 CRES ResourceTemplate in the Persimmon DSDT. This sets up the bus number for the PCI0 device and the secondary bus number in the CRS method. This change came in response to a 'dmesg' error which states: '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS' By adding the 'WordBusNumber' macro, ACPI can set up a valid range for the PCIe downstream busses, thereby relieving the Linux kernel from "guessing" the valid range based off _BBN or assuming [0-0xFF]. The Linux kernel code that checks this bus range is in `drivers/acpi/pci_root.c`. PCI busses can have up to 256 secondary busses connected to them via a PCI-PCI bridge. However, these busses do not have to be sequentially numbered, so leaving out a section of the range (eg. allowing [0-0x7F]) will unnecessarily restrict the downstream busses. This change will apply to other AMD mainboards and will be in a different commit. Change-Id: I44f22bc03a0dcbcd2594d4291508826cc2146860 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2592 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-08AMD Inagua: Use SPD read code from F14 wrapperKimarie Hoot
Changes: - Get rid of the inagua mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: Id05227fcf18c6ab94ffe1beb50b533ab7b0535db Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2607 Reviewed-by: Martin Roth <martin.roth@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-08AMD Persimmon: mainboard.c: Make comment generic to reduce differencePaul Menzel
Replace »persimmon« by »board« in comment to keep `diff` output between boards small. Change-Id: Ieae2a63782c488ae35f22eb30f5b1049200d12c8 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-08AMD Union Station: Use SPD read code from F14 wrapperKimarie Hoot
Changes: - Get rid of the union_station mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I19d6b0d674b67294519383f80928471b37da1e14 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2609 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-08AMD South Station: Use SPD read code from F14 wrapperKimarie Hoot
Changes: - Get rid of the south_station mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: If4291d25ea81bf375f55b64c07c223a847a211d0 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2608 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-07AMD Persimmon: Use SPD read code from F14 wrapperMartin Roth
Changes: - Get rid of the persimmon mainboard specific code which has been moved into the wrapper as a platform generic function in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I5f017dbb8dee5a09ec19734a6069ff9b71a6ab50 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2500 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-03AMD Persimmon, LiPPERT Fam14: Fix typo code*c* in commentPaul Menzel
Commit f154c018 Author: Marc Jones <marcj303@gmail.com> Date: Wed Dec 14 11:24:00 2011 -0700 Persimmon audio codec verb patch. Reviewed-on: http://review.coreboot.org/490 has a typo code*c* in the comments for `AZALIA_OEM_VERB_TABLE`. As this was copied over to the LiPPERT Fam14 boards, use the following command to fix the typo. $ git grep -l cocec | xargs sed -i s,cocec,codec, Change-Id: I1525b0445edab81ab136b3adece52b78ba7abc71 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2576 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-27Persimmon: remove HDMI Audio, PCI device 00:01.1 from devicetree.cbJens Rottmann
Commit 8487229b (Persimmon doesn't have HDMI so the GNB HD Audio should be disabled.) turned off the device in AGESA. Now remove it from devicetree.cb, too. This prevents the following boot message: PCI: Left over static devices: PCI: 00:01.1 PCI: Check your devicetree.cb. Also clarify the line's comment a bit for the Fam14 boards which still retain this device (to counter the loss of information ;-). Change-Id: Ib671ed2e0d04bdef2869e8d70208d6e55cdea3fd Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2537 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-26AMD Inagua: buildOpts.c: Adapt whitespace to coding stylePaul Menzel
Mainly replace spaces by tabs and format comments correctly. Commit »Inagua: Indent and wihtespace cleanup« (f03360f3) [1] was unfortunately incomplete and also used spaces instead of tabs in some cases. Hopefully fix this once and for all to have a template for the other boards. [1] http://review.coreboot.org/547 Change-Id: If15c797581dfefe2a57cd6f26e5bdac4cdd014dd Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2526 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-26AMD Fam14 boards: reduce unnecessary differences, 2nd attemptJens Rottmann
This patch reduces unnecessary differences between AMD Inagua, Persimmon, Union Station, South Station and Asrock E350M1. It's only cosmetical, but makes them a little bit easier to compare. This is the remainder of the original http://review.coreboot.org/2464, parts of which somehow got lost in a flurry of refactoring and splitting patches. Change-Id: I034228be9edaaa4122506763d7bb4158f8e0ec53 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2529 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
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