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2021-02-20AGESA,binaryPI boards: Drop _SI scope with _SST in ASLKyösti Mälkki
Change-Id: I0fca35753c93ba928a0f67bb68a6cfdc26c0e756 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20AGESA,binaryPI boards: Move common PCBA in ASLKyösti Mälkki
Change-Id: I9d502882c4ddb54af1da42a41591804da2cee0ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20AGESA,binaryPI boards: Drop unused variables in ASLKyösti Mälkki
Change-Id: I1d1323ab8bb8565c05fd50697e29c61f9932a2c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20AGESA fam14 boards: Move include for usb_oc.aslKyösti Mälkki
Do this for consistency with later platforms. Change-Id: Ia4903b40a8f617c59868aaa116115fa23603438c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20sb,soc/amd: Drop OSFL method in ASLKyösti Mälkki
Variable OSVR had a static value of 3 and OSFL() did not actually call _OSI or _OS methods. The conditional in HDA _INI method of OSVR is dropped and use of DMA NoSnoop attribute remains disabled to retain previous behaviour. For soc/amd/picasso a different decision was made in CB:40782 as HDA _INI method was just dropped and default configuration enables use of DMA NoSnoop attribute. Change-Id: I967b7b2afbb43253cccb4b77f6c44db45e2989e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50592 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17mainboard/amd/bilby: Add Bilby CRB boardRitul Guru
Bilby is the reference board for AMD Raven, Raven2 and Picasso APUs. Bilby mainboard code is taken from mandolin variant Cereme. These new files are a renamed copy and subsequent patches will be applied to create a working bilby implementation. Change-Id: I426966d782e259a971ec36bac2498bc62b4ce7e2 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-15src: use ARRAY_SIZE where possiblePatrick Georgi
Generated with a variant of https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14sb/amd/cimx/sb800: Move common OSFL method in ASLKyösti Mälkki
We deal with mb/lippert/frontrunner-af later since it currently does not include <cimx/sb800/acpi/fch.asl>. Change-Id: I30b611fc1fb01777223d7222adc96308a247a35c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50591 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14AGESA,binaryPI boards: Drop OSV in ASLKyösti Mälkki
Not referenced anywhere in ASL. Change-Id: I52ac4722e48e1cc377386316dc034fb45a98181a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50471 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/cezanne: move CPU cluster to chipset device treeFelix Held
This will be common for all boards, so move it to the chipset device tree. TEST=CPU cluster and LAPIC still show up in console logs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia49e7b4cfc09c60b6152b8ccc47f37b6adc1e319 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50613 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14mb/amd/majolica/mainboard: Set ACPI IRQRaul E Rangel
We now pass the ACPI SCI IRQ to the OS, so make sure the board routes it correctly. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1b4d5e0bfb1d9df9ac8a8c41cdf466a67f2673d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-02-13mb/amd/majolica: Add plain dsdtRaul E Rangel
Needed to enable ACPI support for cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifd71635d3493e0cf104b60ecf94ebdf70d512b94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12mb/amd/majolica/devicetree: add CPU clusterFelix Held
Change-Id: I8d8b7f3ea2502e4e49a1290b07d84d5bbb2924a7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50506 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12soc/amd: Move fadt device tree settings into common_configRaul E Rangel
This is ACPI specific config that applies to all the AMD SoCs. Stoney doesn't currently use this, but we can add that functionality later. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12mb/amd/majolica: Add FCH IRQ routingRaul E Rangel
I left most everything as NC since we don't expose the values to the OS yet. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7c3195ef27091f1bc61892c475ffe09137b63083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50511 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11ACPI: Move PICM declarationKyösti Mälkki
Variable PICM was not inside GNVS region and can use a static initialisation value. For most AMD platforms PICM default changes from 1 to 0. Fix comments about PICM==0 used to indicate use of i8259 PIC for interrupt delivery. Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11mb/amd/majolica: Add chromeos supportRaul E Rangel
This change enables vboot support. To use it add CHROMEOS=y to your config. TEST=Boot majolica and see verstage run, and then see depthcharge load. coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 verstage starting (log level: 8)... Phase 1 FMAP: area GBB found @ 805000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 Phase 2 Phase 3 FMAP: area GBB found @ 805000 (458752 bytes) FMAP: area VBLOCK_A found @ 30000 (8192 bytes) FMAP: area VBLOCK_A found @ 30000 (8192 bytes) VB2:vb2_verify_keyblock() Checking keyblock signature... VB2:vb2_verify_digest() HW RSA forbidden, using SW VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW FMAP: area VBLOCK_A found @ 30000 (8192 bytes) FMAP: area VBLOCK_A found @ 30000 (8192 bytes) VB2:vb2_verify_fw_preamble() Verifying preamble. VB2:vb2_verify_digest() HW RSA forbidden, using SW VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW Phase 4 FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes) VB2:vb2api_init_hash() HW crypto forbidden by TPM flag, using SW VB2:vb2_verify_digest() HW RSA forbidden, using SW VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW Saving secdata firmware Saving secdata kernel Saving nvdata Slot A is selected FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes) CBFS: mcache @0x02017000 built for 9 files, used 0x1ec of 0x800 bytes CBFS: Found 'fallback/romstage' @0x0 size 0x753c in mcache @0x02017000 BS: verstage times (exec / console): total (unknown) / 116 ms coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 romstage starting (log level: 8)... Family_Model: 00a50f00 FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes) CBFS: Found 'fspm.bin' @0x15440 size 0x2257d in mcache @0x02017138 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I43f0c6e33649332057f41f8813a86571b06032f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-11mb/amd/mandolin/Kconfig: Remove unneeded whitespace before tabElyes HAOUAS
Change-Id: I2b52c32a607386cdc1ca00531eda4dfc0bfaab1e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10mb/amd/gardenia: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I8c8845ed6eb466acff568247184c6ad6b186e9ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46145 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/olivehill: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Icacd8c8a7b5604354a7fd04ed73ecb3bbc86e669 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46147 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/persimmon: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I492118c9287b5853e8784a6de6bc514e97c93e96 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46150 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/south_station: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I52c33679fbb7e9807423fc0fcc470e54105013db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46151 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/union_station: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl are identical. Change-Id: I8127b5b22e2822f4ace07c28409e501c3fcb309b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46153 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/inagua: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I0ee0d2b83cbfd81fab43eec255bcc214b9543f82 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46146 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04src: Remove useless comments in "includes" linesElyes HAOUAS
Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04mb/amd/{parmer,thatcher}/bootblock.c: Remove unused includesElyes HAOUAS
Change-Id: I4d5520649addc671527e75f9090ea45a83b5db9b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-04mb/amd/majolica: add fmd for use when building chromeosMathew King
BUG=b:177909472 TEST=builds Change-Id: I5eb3c60fe60e4029485fae642c88c5c013ffb3f6 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50208 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-02treewide [Kconfig]: Remove useless commentElyes HAOUAS
Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-30mb/amd/majolica: Add an empty bootblock function to handle GPIOZheng Bao
Change-Id: I35da3812a424ea1beef86d043a756a87e6afdaa3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50117 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30mb/amd/majolica: Add an empty function of mainboard bootblockZheng Bao
Change-Id: I985405b51c81d1e5a3a593bfb759e9850beb2244 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-28mb/amd/thatcher: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: If1869d091f9c78db7e308143d96b5d3046510ac8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46152 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/amd/parmer: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I563cd549858429049223677ebc503f9c9304baa0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46149 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/amd/padmelon: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I88c1c907916c3de51f6b3b72f7a49e90a1b1a383 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46148 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28Revert "mb/amd/mandolin: Clean up IRQ numbers"Felix Held
This reverts commit 2a1638a9cead257115ff82b18862d506015378b2. The original commit broke Mandolin and with the revert applied, I can boot into Linux via SeaBIOS again. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7024b6ff1e772bbc89f810c766655a5887ed8b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49950 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-27sb,soc/amd: Rename PMOD to PICM in ASLKyösti Mälkki
Use the same variable name as soc/intel to implement a common _PIC method at top-level ASL. Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-22mb/amd/majolica: Add PSP support for board majolicaZheng Bao
Change-Id: Ia2470a7297c7003c7975c7d9b977f2f97174efea Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48529 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-19soc/amd/picasso: move HAVE_ACPI_TABLES from mainboards to SoCFelix Held
The SoC code has in implicit dependency on this option, so select it in the SoC code instead of the mainboard code. Change-Id: Iea908c142f4a94a107cf74a31d9f5e29668d4b5b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-18mb/amd/majolica: Add option of ROM sizeZheng Bao
Change-Id: I07740285658aa098d3785cbead173b2f3acca42d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-15build system: Always add coreboot.pre dependency to intermediatesPatrick Georgi
They all operate on that file, so just add it globally. Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15mb/amd/mandolin: Clean up IRQ numbersRaul E Rangel
We no longer need the IO-APIC assignments since we use the GNB IO-APIC. We were also missing the E-H IRQ mapping. I also renumbered them since IRQ 8 is used by the rtc. TEST=none BRANCH=zork Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia956ae457669aeda6fa49e127373aad3807f7b9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/49368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-14build system: Structure and serialize INTERMEDIATEPatrick Georgi
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14mb/amd/majolica: use integrated UART as consoleFelix Held
Change-Id: Ic6dcbe999234f233fbac8fbdb06d22c8577b1a40 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-06mb/amd/mandolin/mainboard: Remove unused pirq_dataRaul E Rangel
This table was wrong. It's also produced by the SoC code now. BUG=b:170595019 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifcc406591abf88ebdb5ed972614c3a6901721bac Reviewed-on: https://review.coreboot.org/c/coreboot/+/48667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-16soc/amd/picasso: Fix the typo in GPIO defineZheng Bao
Change-Id: I8c9eed5d0e320b02382c24304a44e51e89eb6ac5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-11soc/amd/cezanne: add 0xcf9 resetFelix Held
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/amd/picasso: rename PICASSO_CONSOLE_UART to AMD_SOC_CONSOLE_UARTFelix Held
This allows factoring out the common initialization for the integrated UARTs. Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48508 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05mb/amd/majolica: add functionality to add EC blob to buildFelix Held
Without the EC blob being present in the SPI flash, the board won't even power up. Change-Id: Ia3c50e86414bbc707bc33e28c636196c1be2f1e6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-05mb/amd/majolica: add skeleton of Cezanne reference boardFelix Held
This is an adapted copy of mainboard/example/min86 that is currently only used for Jenkins to test the SoC code in soc/amd/cezanne and isn't expected to reach boot block at the moment. It will be extended in future follow-up commits. Change-Id: I6806955952fbfa3227294cfc44fdf9156140e933 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04mb/amd/mandolin: Unify devicetree formatting for 00:14 devicesPaul Menzel
To accommodate also `off`, two spaces are used after `on` to align comments. This unifies the devicetree files of the two variants. Change-Id: I7908fe2313ddccb6a4448a6338d6cd4938264f62 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04mb/amd/mandolin: mandolin: Fix typo in *Coprocessor* in commentPaul Menzel
This reduces the difference with Cereme’s devicetree file. Change-Id: I1e6ba5891245562d5132307eab224623031e11c8 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04mb/amd/mandolin: use more readable size formats in FMAP filesFelix Held
Since the FMD file isn't parsed any more by a shell script in the SoC's Makefile.inc, we can use better human-readable numbers for the section sizes. TEST=Timeless build results in identical image. Change-Id: I2117064a694f67767284f6fd4ac3604b254a2734 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04mb/amd/mandolin: removed unused MANDOLIN_MICROCHIP_FW_OFFSETFelix Held
TEST=Timeless build results in identical image. Change-Id: Ifa5c14add555b382f74ba1165131b1569bbef123 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-30soc/amd/picasso: remove PICASSO_LPC_IOMUX Kconfig option from SoCFelix Held
PICASSO_LPC_IOMUX was only used in the amd/mandolin board, but not in the corresponding SoC code, so remove it from the SoC's Kconfig and reanme it in the mainboard's Kconfig to MANDOLIN_LPC. Change-Id: I261e093d6c56be6073a816b79c60d3a0457616f8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-25mb/amd/mandolin: Add decode range for LPC debug cardNikolai Vyssotski
Some LPC debug boards hard strap SIO address to be at 0x164e/0x164d vs 0x4e/0x4d. Add support for configurable SIO address to support these cards. BUG=b:159933344 TEST=boot with LPC debug card, verify serial output Change-Id: I103c61f21f13970dfa3b9a788b29964e478fb84c Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-23mb/google/zork: correct USB2 phy TXVREFTUNE0 parameter nameKevin Chiu
From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0". correct rx_vref_tune -> tx_vref_tune BUG=None BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-23mb/**/cmos.layout: Indent everything with tabsAngel Pons
Time has shown that using spaces never converges into proper alignment. Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-11-23mb/**/cmos.layout: Remove crusty commentsAngel Pons
Most of these comments have been copy-pasted or serve no purpose other than to eventually turn into misleading info. While the description of the first 120 bits of CMOS could be useful, it should instead be added to the documentation for the CMOS option infrastructure, or /dev/null. Moreover, trim down newlines to no more than two consecutive newlines. Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-11-12mb/amd/mandolin/Kconfig: update help text for AMD_LPC_DEBUG_CARDFelix Held
The existing help text wasn't updated for Mandolin after it was copied from an older reference board and contained some information that doesn't apply to Mandolin. Change-Id: Ib34abb2ee8b289df5f7085957042fe00ad506ca9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-12mb/amd/mandolin/Kconfig: add help text for the EC blobFelix Held
Change-Id: If8d3ebdb9a41330312c26fb5796c07de1b87b3eb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47480 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-05soc/amd/picasso: move MAX_CPUS setting from mainboard to SoC KconfigFelix Held
Since the mainboard Kconfig is sourced before the SoC one, it would still be possible to override this setting at mainboard level, even though that shouldn't be needed. The maximum CPU count for Picasso is 8, since the chips have only up to 4 cores with up to two threads each. Change-Id: I53449b8fa73c5d13e6ea77bee6eed8896b7d3ec3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47205 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17mb: AMD CIMx boards: Fix typo in *is defined* in commentsPaul Menzel
The passive clause is constructed with the past participle, which is *defined* in this case. Fix all occurrences in AMD vendor code with the command below. git grep -l "is define at" src/mainboard/ | xargs sed -i 's/is define at/is defined at/' Change-Id: I5aa0e6e064410b305aa5f2775271f6a8988da64b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46066 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17AGESA mb: Replace tab with space in macro definition for consistencyPaul Menzel
With a tabulator length of eight spaces, the alignment is the same, but the other macro definitions are using a space, so do the same for consistency, better alignment in diff views. git grep -l -P 'define\tBLD' | xargs sed -i 's,define\tBLD,define BLD,g' Change-Id: Ib71057c84dc897028cb0ceac29952e67bc541d2e Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-13mb/*/*/dsdt.asl: Drop useless comments in DefinitionBlock()Elyes HAOUAS
Change-Id: I1e0489ec6730760f74102cdd00e4aaa66975d69a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13mainboard/*/*/dsdt.asl: Make DefinitionBlock's AMLFileName uniformElyes HAOUAS
Make output AML file name uniform. Change-Id: Ic6cac4748a6159c695888b2737ada677d91f4262 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-13{src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-30mb/amd: Add Pollock CRB Cereme as Mandolin variantFelix Held
Even though the devicetrees of Mandolin and Cereme are relatively similar, they are kept as separate files instead of using devicetree overrides to facilitate creating mainboard ports based on those CRBs. The two boards are reference boards for different zen/zen+ APU platforms that share the silicon, but use different packages. This is also consistent with the google/zork boards that have two different full base devicetrees for the two different platforms and then use devicetree overrides for the different variants of the two reference designs. BUG=b:159617786,b:169644059 BRANCH=zork Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42786 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30mb/amd/mandolin: change EFS SPI mode from 1-4-4 to 1-1-4Felix Held
With this change the flash addresses will only get transferred over one data pin like in the non-quad SPI mode and only the data will get sent over all four data pins. Since this gives the flash chip a bit more time to fetch the data the host requested, this allows higher SPI frequencies resulting in a higher throughput when bigger chunks of memory get read. BRANCH=zork Change-Id: Iad4c922ffcdba4b17e6e81244ff37302eb171d97 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45831 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30mb/amd/mandolin: add missing SPI configuration to devicetreeFelix Held
This fixes the board not booting reliably when running from flash without the EM100 option selected during build time. Selecting EM100 mode overrides the settings, so when testing with an EM100 I didn't run into this issue. BUG=b:169644059 BRANCH=zork Change-Id: I2c7043c174dcf4501776a03b7689d8a20c214afb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45830 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23mb/amd/mandolin: simplify flashmap fileFelix Held
Now that we're using fmaptool to parse the .fmd file, we can use some short forms and omit unnecessary information. BUG=b:157068645 TEST=Timeless build for amd/mandolin resulted in identical binary. BRANCH=zork Change-Id: I196c7857f165e75b543c1bda650e044b5ad0664e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-21mb/amd: Drop unneeded empty linesElyes HAOUAS
Change-Id: I2ceeae8dd25663203549a87b4e9524a631fa92f8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-14src/mainboard: Remove unused include <device/pnp_ops.h>Elyes HAOUAS
Change-Id: I278fb20aa176bb09f1ff135fdfd732f0096d3808 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14mb/amd/olivehill/bootblock.c: Add missing <arch/io.h>Elyes HAOUAS
Change-Id: I75ea4fc71cf22e5ad547329db2451342cee528b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14soc/amd/picasso: Move sd_emmc_config into emmc_config structRaul E Rangel
I plan on adding another eMMC parameter. This refactor keeps the config contained in a single struct. BUG=b:159823235 TEST=Build test Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-10soc/amd/picasso: Move APCB generation out of picassoRob Barnes
Move APCB generation out of the picasso makefile and into the mainboard makefile. APCB generation tends to be mainboard specific and does not belong in the soc makefile. BUG=b:168099242 TEST=Build mandolin and check for APCB in coreboot binary Build and boot ezkinil Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
BOOTBLOCK_CONSOLE is already set to yes in console/Kconfig file. Change-Id: I2a4ee517795bc7b378afc5eae92e2799ad36111b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-31mb/amd/mandolin: move PCIe GPP clock setting to devicetreeFelix Held
Checked with the schematics that all PCIe clocks have a corresponding clock enable pin. BUG=b:149970243 BRANCH=zork Change-Id: If96cdf95e213682217e46a98fc69c5c2ef4a148d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44892 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/amd: Drop unneeded empty linesElyes HAOUAS
Change-Id: Ib82689150689716bc9afdf8d4527a1dcd5deae56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-24mb/amd/mandolin: fix AUX/HDP mapping for last DDI port on DaliFelix Held
We hit a similar issue on Cereme, so I checked the trembyle base board which also uses AUX4/HDP4 for the last DDI port, so using AUX3/HDP3 is wrong there. Change-Id: I99f9426969488cc5c5a14bd432b38bfd69ae7ef0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2020-08-18mb/amd/mandolin: enable SoC UARTs 0 and 1 and disable 2 and 3Felix Held
There are only headers for the SoC's UART 0 and 1 on the board. BUG=b:165020060 TEST=Linux only detects UART 0 and 1. Change-Id: I45929f65a5f844ae5cef792b11176f487c80766f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44530 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18mb/amd/mandolin: select ACPI driver for internal memory mapped UARTsFelix Held
In order for Linux to find and use the SoC's integrated UARTs, they need to be exposed in ACPI. BUG=b:165020060 TEST=Linux detects the SoC's integrated UARTs. Change-Id: Iaa66657b88f62b2067c865c3e1945b7bdbf9be23 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-18mb/amd/mandolin: use SoC UART for console if LPC UART isn't presentFelix Held
Using the SOC's UART 0 as console requires moving a few resistors on the Mandolin board. BUG=b:165020060 TEST=coreboot console works on SoC UART 0 when AMD_LPC_DEBUG_CARD isn't selected. Change-Id: Idaf73ae84f54028da2182ce42035f9ecd63f4776 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-15mb: remove unnecessary FADT flag devicetree entries for PicassoFelix Held
Those flags already get unconditionally set in soc/amd/picasso/acpi.c. Change-Id: I978c7d67480499d92c193d5bb87bc876211187db Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-04mb/**/{devicetree,overridetree}.cb: Indent with tabsAngel Pons
Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-30mb/amd,google/mandolin,zork: Set EFS SPI platform configMatt Papageorge
Set platform defaults for SPI settings in Kconfig for EFS. BUG=b:158755102 TEST=Build and boot test on Tremblye and Morphius. Verify values in output image in a hex editor. Measure 1st x86 timestamp, perf improves by over a second. Change-Id: I765dada14700f4800263d2d3844af07fad0e5b71 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/amd/mandolin: remove ACPI_FADT_RESET_REGISTER from fadt_flagsFelix Held
This applies what commit 79572e4f32f844f60338d1aafdba6b94f4111a5c does to the devicetree settings of amd/mandolin. Change-Id: I6cc0a2b60b13a809016225caf3c89f730deb4ce0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-27mb/amd/mandolin: add USB over-current pin mapping to devicetreeFelix Held
The over-current pin mapping matches the board schematics. Change-Id: I23fd208680dcb52f5adaa144f00cb46bc7a21b91 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26Kconfig: Remove unnecessary choice namesMartin Roth
The only reason to use a named choice statement is if you plan on having the choice statement in multiple places. Since none of these are used in multiple places, we can get rid of the names. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie5f84e9dc38050234976bd193ac5fbf649e564f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26mb/amd/mandolin: add default USB2 PHY tune parameters to devicetreeFelix Held
Change-Id: I4ea2fb83522d8810fe84e0a3f42bf44f2f911461 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43819 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23amd/picasso: rename PCIe descriptor to DXIO descriptorFelix Held
Most of the DXIO descriptors are used to configure PCIe engines and lanes, but on Picasso system some of the DXIO lanes can also be configured as SATA or XGBE ports. Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23vc/amd/fsp/picasso: add logical to lane number in port descriptor structFelix Held
The lane numbers in the PCIe/DXIO descriptor are the logical and not the physical ones, so add logical to the corresponding field names of the fsp_pcie_descriptor struct. Change-Id: I7037fed225119218e87593932815aff815e83ff8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-22mainboard/amd/mandolin: describe where the two HDA codecs resideFelix Held
Change-Id: I99b062e4ce1cf862ea03b0edb6ea843df5f8f2b2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-20mb/amd/mandolin: Delete sleep.aslRaul E Rangel
These methods are empty and the kernel treats these as optional. BUG=b:153001807, b:154756391 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic8ee8fb6b6bcd04c653ab77cdc5e746a8cbd0c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43466 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/amd/mandolin: Drop mainboard.aslFurquan Shaikh
This change drops mainboard.asl from zork because none of the objects defined in it are used. Change-Id: I879b5614fb5d12c4814ee52f840a000744a7aab9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43520 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Move PMOD global variable to globalnvs.aslFurquan Shaikh
Global variable `PMOD` that stores the interrupt mode used by OS is required by all mainboards. This change moves the variable definition to globalnvs.asl under picasso. Additionally, ACPI spec says that BIOS should assume interrupt mode as PIC until _PIC() method is called by OS. Thus, this change also updates the default value of PMOD as 0 i.e. PIC mode. BUG=b:153879530 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I731c03d965882281a7a23f55894451210ba72274 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43514 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/picasso: remove unused fadt_pm_profile devicetree settingFelix Held
commit 56da63c3dc3f50cfac541c779b608e1bae9e635c removed overriding that field in the FADT. Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/amd/mandolin: add SATA DXIO descriptor for Dali SKUsFelix Held
Dali supports two SATA ports, but no PCIe alternate function on those pins. Change-Id: I27a13100e80565eb1dade2d703ba3d1f8b5f630f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16mb/amd/mandolin: fix DXIO lane numbersFelix Held
The DXIO descriptors use the logical and not the physical lane numbers, which are different. Change-Id: I7a90056d782d8d32fe34a0f5bdb61c3b61df1af8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing PciExpWakeStatusRaul E Rangel
The kernel already clears this: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/acpi/acpica/hwregs.c;l=390 No reason to have the firmware do it as well. BUG=b:153001807, b:154756391 TEST=Build Trembyle, boot, suspend, and resume and didn't see any ACPI errors. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia5c79fb95dc885eaef8abc4257b6ba18c1ef1b66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16soc/amd/picasso,mb/{zork,mandolin}: Remove invalid UPWS variableRaul E Rangel
PMx0EE is not defined in the Picasso PPR. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98caf0cd2d0bdcf19de2b945dcf74f5cf7354769 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 00:41:40 +0000