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2022-03-30mb/amd/chausie/port_descriptors: update DDI descriptorsFelix Held
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I31db6c138a21dc22e7aa473f2215ca2c7594326c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63163 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30mb/amd/chausie/devicetree: update PCI root portsFelix Held
Only enable the PCIe root ports that have corresponding DXIO descriptors and also update the comments to have them match the actual hardware configuration. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I378c620abb6e52de680669b6edd228874153e399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63162 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30mb/amd/chausie/port_descriptors: update DXIO descriptorsFelix Held
Change the DXIO descriptors to match the default PCIe lane mapping on the chausie board. With this configuration and a board-level rework to bypass the EC control of the NVMe SSD power supply rail, this configuration results in the SSD being detected on the root port on bus 0 device 2 function 3 and usable as boot device. This was also validated against the schematics revision B. Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib74988b741f748d240ef09fa0dba8885bdc5e706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63161 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-25mb/*/BiosCallOuts.c: Fix unused variableArthur Heymans
This fixes clang builds. Change-Id: Ie09fae149a9530ad45f0cd5945e73f46484ef385 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-23soc/amd/cezanne: Turn off gpp clock request for disabled devicesRobert Zieba
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled. BUG=b:202252869 TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled, checked that physically removing a device that is marked as enabled also disables the corresponding clk req BRANCH=guybrush Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-21mb/amd/chausie: add APCB binaries if availableFelix Held
The APCB files that provide the firmware components running on the PSP some mainboard-specific information like the DRAM interface configuration. Those files aren't yet in the upstream 3rdparty/blobs repository, so only add those files if they are present and print that no APCB was added and the image won't boot if they aren't present. TEST=Both cases behave as expected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-21mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MBNikolai Vyssotski
To have enough space in the A/B RW sections, increase those sizes to 4 MByte and decrease the RO section size to 6 MByte to free up the space needed for that. Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-19mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLEDFelix Held
Right now, the PSPP policy that controls if the PCIe lanes can be dynamically downgraded to a lower speed to save some power needs to be disabled in order for the link training to be successful. Once this feature is working, the PSPP policy will be switched to balanced again. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-14mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devicesFelix Held
GFX HDA is the audio controller that provides audio output via the external display connection, ACP is the audio coporcessor for the on- board audio codec and XHCI2 is the third XHCI controller that provides one USB 2.0 port. All those devices are used, so enable them in the board's devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62571 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-03soc/amd/stoneyridge/acpi: rename cpu.asl to pnot.aslFelix Held
After the patch that moved the generation of the PPKG object to Stoneyridge's acpi.c, only the PNOT object remained in its cpu.asl, so rename it to pnot.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/picasso/acpi: rename cpu.asl to pnot.aslFelix Held
After the patch that moved the generation of the PPKG object to Picasso's acpi.c, only the PNOT object remained in its cpu.asl, so rename it to pnot.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-01mb/amd/chausie: Always enable developer modeRaul E Rangel
Chausie doesn't have recovery mode buttons so it's impossible to manually enter recovery mode to enable developer mode. This means we need to force developer mode. BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id0b08ee8e009e8603f63e691b5a7a2ac04e1fc3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-28mb/amd/chausie/Kconfig: Add EC FW to RO_REGION_ONLYFred Reitberger
Include chausie EC and EFS only in the RO region when building with vboot. Without this, the EC is also added to the FW_MAIN_A and FW_MAIN_B regions. Change-Id: I78de8bd639232b9fb6d775b77ecd892f28514614 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-25mb/amd/chausie/devicetree: add i2c_scl_resetFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23ec6bcb6a2b3627866165972fd6ba1c75367533 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62188 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25mb/amd/chausie/devicetree: enable I2C controllersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97f37c45ffe945e6bb071c8205343943edc524ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61871 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21mb/amd/chausie/chromeos.fmd: resize EC size in FMAP to 4kByteFelix Held
Only the info about the location of the EC firmware will be stored right at the beginning of the flash, so the size can be reduced to 4kByte which is the erase block size of the flash. The CHAUSIE_MCHP_SIG_FILE file itself is smaller than this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icde5f7071183cd8423fc022caf49e2c9ee288527 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62189 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21mb/amd/chausie/Kconfig: Move EC firmware image in CBFSFred Reitberger
Move the EC to a location that does not conflict with where the main CBFS is in the chromeos FMAP Change-Id: I28c84cbe2ff10d45383d896ae4f942ee49eb15c0 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62190 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-19mb/amd/chausie: increase RW_MRC_CACHE size in FMAPFelix Held
On Sabrina SoCs the size of the APOB has increased, so the size of the RW_MRC_CACHE FMAP sections needs to be increased in order for the data to still fit in the corresponding FMAP partition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib31b918aba90dd507b47aec9e1f75c138857cd02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62155 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17mb/amd/chausie: Add EC blob into CBFSFred Reitberger
Add chausie EC blob into CBFS at specified location Change-Id: I48de08a18054efbda655e1563a539ff2ba7a38a6 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15mb/amd/chausie: initialize KBRST and EC flash sharing pins in bootblockFelix Held
The SPI ROM REQ/GNT pins are used in systems where the EC and the APU share one flash chip to make sure that not both devices will try to access the flash at the same time. The firmware running before the x86 cores are released from reset has likely already done this, but do it again in bootblock just to be sure. The KBRST_L pin can be used to reset the APU from the EC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5af285ac222ed6625f498d82360f2d1cc522df2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-13mb/amd/chausie: update GPIO for chausieFred Reitberger
Add/update initial GPIO pin descriptions and initialization types for chausie mainboard. Change-Id: I14ea0e1086f626398a867896ee81ce07cf530182 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-12mb/amd/majolica/mainboard: add initial IRQ routingFelix Held
This IRQ routing info is taken from mb/google/guybrush. The IRQ routing on Chausie that was a 1:1 copy caused some issues with the I2C driver, so port the Chausie IRQ mapping change back to Majolica. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieb958639dd8aef7c60c050ad107dde7d1cd6a8bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12mb/amd/chausie/mainboard: add initial IRQ routingFelix Held
This IRQ routing info is taken from mb/google/guybrush. This should fix these errors: [ 0.655051] i2c_designware AMDI0010:00: IRQ index 0 not found [ 0.659239] i2c_designware AMDI0010:01: IRQ index 0 not found [ 0.663198] i2c_designware AMDI0010:02: IRQ index 0 not found [ 0.667200] i2c_designware AMDI0010:03: IRQ index 0 not found Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8c85c8e4b1c860d6ca25060353355f703a49e1e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-04soc/amd/sabrina/include/amd_pci_int_defs.h: remove PIRQ_SATAFelix Held
Sabrina has no SATA controller, so remove the corresponding PIRQ mapping. This was verified with PPR #57243 Rev 1.53. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I98ffa3675c361e8a74c50ebfc37e79ae63dacc85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03mb/amd/chausie/devicetree: update I2C RX levels to match board designFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie5d5f5441132e5b0d8991d07d4dde994fc17ab64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03soc/amd/*/i2c: factor out common I2C pad configurationFelix Held
The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-31mb/amd/majolica: Add variant to disable HDMIZheng Bao
For one specific type of APU, it doesn't have HDMI. When we detect this APU, we need to explicitly disable HDMI in DDI settings, otherwise the system would freeze. Please refer src/mainboard/google/guybrush/variants/dewatt/variant.c Change-Id: I8d7637467d2f16377d3c3064cdb0934d1658fdf7 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-27soc/amd/sabrina/chipset.cb: update USB portsFelix Held
The corresponding mainboard design guide was used as a reference here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie61af7dab35b560d2eec1ea62058f3a4dad5cb0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina: update PCI devices in devicetree.cbFelix Held
Also update mb/amd/chausie accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb4dcffa48c3dbdcffb66f1398b99ee96562efb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25mb/amd/chausie: add mainboard as copy of mb/amd/majolicaFelix Held
To have the new AMD Sabrina SoC code tested, add the AMD Chausie mainboard as a copy of Majolica. This patch also changes the name from Majolica to Chausie, selects the Sabrina SoC instead of the Cezanne SoC and comments out the APCB_SOURCES since those aren't available in the 3rdparty/blobs repository yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic7b18f7a6ae5b8365234dd1227e0b1f7f37279da Reviewed-on: https://review.coreboot.org/c/coreboot/+/61079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-10src/mainboard/amd: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Ie06cfa598f40a734994abb2bc2eb8f01f9331f7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/mainboard/{amd,roda}: Remove unused <acpi/acpi.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <acpi/acpi.h>' -- src/) <(git grep -l 'SLP_EN\|SLP_TYP_SHIFT\|SLP_TYP\|SLP_TYP_S\|ACPI_TABLE_CREATOR\|OEM_ID\|ACPI_DSDT_REV_\|acpi_device_sleep_states\|ACPI_DEVICE_SLEEP\|RSDP_SIG\|ASLC\|ACPI_NAME_BUFFER_SIZE\|COREBOOT_ACPI_ID\|acpi_tables\|acpi_rsdp\|acpi_gen_regaddr\|ACPI_ADDRESS_SPACE\|ACPI_FFIXEDHW_\|ACPI_ACCESS_SIZE_\|ACPI_REG_MSR\|ACPI_REG_UNSUPPORTED\|ACPI_HID_\|acpi_table_header\|MAX_ACPI_TABLES\|acpi_rsdt\|acpi_xsdt\|acpi_hpet\|acpi_mcfg\|acpi_tcpa\|acpi_tpm2\|acpi_mcfg_mmconfig\|acpi_hmat\|acpi_hmat_mpda\|acpi_hmat_sllbi\|acpi_hmat_msci\|acpi_srat\|ACPI_SRAT_STRUCTURE_\|acpi_srat_lapic\|acpi_srat_mem\|acpi_srat_gia\|CPI_SRAT_GIA_DEV_HANDLE_\|acpi_slit\|acpi_madt\|acpi_lpit\|acpi_lpi_flags\|acpi_lpi_desc_type\|ACPI_LPI_DESC_TYPE_\|acpi_lpi_desc_hdr\|ACPI_LPIT_CTR_FREQ_TSC\|acpi_lpi_desc_ncst\|acpi_vfct_image_hdr\|acpi_vfct\|acpi_ivrs_info\|acpi_ivrs_ivhd\|acpi_ivrs\|acpi_crat_header\|ivhd11_iommu_attr\|acpi_ivrs_ivhd_11\|dev_scope_type\|SCOPE_PCI_\|SCOPE_IOAPIC\|SCOPE_MSI_HPET\|SCOPE_ACPI_NAMESPACE_DEVICE\|dev_scope\|dmar_type\|DMAR_\|DRHD_INCLUDE_PCI_ALL\|ATC_REQUIRED\|DMA_CTRL_PLATFORM_OPT_IN_FLAG\|dmar_entry\|dmar_rmrr_entry\|dmar_atsr_entry\|dmar_rhsa_entry\|dmar_andd_entry\|dmar_satc_entry\|acpi_dmar\|acpi_apic_types\|LOCAL_APIC,\|IO_APIC\|IRQ_SOURCE_OVERRIDE\|NMI_TYPE\|LOCAL_APIC_NMI\|LAPIC_ADDRESS_\|IO_SAPIC\|LOCAL_SAPIC\|PLATFORM_IRQ_SOURCES\|LOCAL_X2APIC\|GICC\|GICD\|GIC_MSI_FRAME\|GICR\|GIC_ITS\|acpi_madt_lapic\|acpi_madt_lapic_nmi\|ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS\|acpi_madt_ioapic\|acpi_madt_irqoverride\|acpi_madt_lx2apic\|acpi_madt_lx2apic_nmi\|ACPI_DBG2_PORT_\|acpi_dbg2_header\|acpi_dbg2_device\|acpi_fadt\|ACPI_FADT_\|PM_UNSPECIFIED\|PM_DESKTOP\|PM_MOBILE\|PM_WORKSTATION\|PM_ENTERPRISE_SERVER\|PM_SOHO_SERVER\|PM_APPLIANCE_PC\|PM_PERFORMANCE_SERVER\|PM_TABLET\|acpi_facs\|ACPI_FACS_\|acpi_ecdt\|acpi_hest\|acpi_hest_esd\|acpi_hest_hen\|acpi_bert\|acpi_hest_generic_data\|acpi_hest_generic_data_v300\|HEST_GENERIC_ENTRY_V300\|ACPI_GENERROR_\|acpi_generic_error_status\|GENERIC_ERR_STS_\|acpi_cstate\|acpi_sw_pstate\|acpi_xpss_sw_pstate\|acpi_tstate\|acpi_lpi_state_flags\|ACPI_LPI_STATE_\|acpi_lpi_state\|acpi_upc_type\|UPC_TYPE_\|acpi_ipmi_interface_type\|IPMI_INTERFACE_\|ACPI_IPMI_\|acpi_spmi\|ACPI_EINJ_\|ACTION_COUNT\|BEGIN_INJECT_OP\|GET_TRIGGER_ACTION_TABLE\|SET_ERROR_TYPE\|GET_ERROR_TYPE\|END_INJECT_OP\|EXECUTE_INJECT_OP\|CHECK_BUSY_STATUS\|GET_CMD_STATUS\|SET_ERROR_TYPE_WITH_ADDRESS\|TRIGGER_ERROR\|READ_REGISTER\|READ_REGISTER_VALUE\|WRITE_REGISTER\|WRITE_REGISTER_VALUE\|NO_OP\|acpi_gen_regaddr1\|acpi_einj_action_table\|acpi_injection_header\|acpi_einj_trigger_table\|set_error_type\|EINJ_PARAM_NUM\|acpi_einj_smi\|EINJ_DEF_TRIGGER_PORT\|FLAG_PRESERVE\|FLAG_IGNORE\|EINJ_REG_MEMORY\|EINJ_REG_IO\|acpi_einj\|acpi_create_einj\|fw_cfg_acpi_tables\|preload_acpi_dsdt\|write_acpi_tables\|acpi_fill_madt\|acpi_fill_ivrs_ioapic\|acpi_create_ssdt_generator\|acpi_write_bert\|acpi_create_fadt\|acpi_fill_fadt\|arch_fill_fadt\|soc_fill_fadt\|mainboard_fill_fadt\|acpi_fill_gnvs\|acpi_fill_cnvs\|update_ssdt\|update_ssdtx\|acpi_fill_lpit\|acpi_checksum\|acpi_add_table\|acpi_create_madt_lapic\|acpi_create_madt_ioapic\|acpi_create_madt_irqoverride\|acpi_create_madt_lapic_nmi\|acpi_create_madt\|acpi_create_madt_lapics\|acpi_create_madt_lapic_nmis\|acpi_create_madt_lx2apic\|acpi_create_srat_lapic\|acpi_create_srat_mem\|acpi_create_srat_gia_pci\|acpi_create_mcfg_mmconfig\|acpi_create_srat_lapics\|acpi_create_srat\|acpi_create_slit\|acpi_create_hmat_mpda\|acpi_create_hmat\|acpi_create_vfct\|acpi_create_ipmi\|acpi_create_ivrs\|acpi_create_crat\|acpi_create_hpet\|acpi_write_hpet\|generate_cpu_entries\|acpi_create_mcfg\|acpi_create_facs\|acpi_create_dbg2\|acpi_write_dbg2_pci_uart\|acpi_create_dmar\|acpi_create_dmar_drhd\|acpi_create_dmar_rmrr\|acpi_create_dmar_atsr\|acpi_create_dmar_rhsa\|acpi_create_dmar_andd\|acpi_create_dmar_satc\|cpi_dmar_\|acpi_create_\|acpi_write_hest\|acpi_soc_get_bert_region\|acpi_resume\|mainboard_suspend_resume\|acpi_find_wakeup_vector\|ACPI_S\|acpi_sleep_from_pm1\|acpi_get_preferred_pm_profile\|acpi_get_sleep_type\|acpi_get_gpe\|permanent_smi_handler\|acpi_s3_resume_allowed\|acpi_is_wakeup_s3\|acpi_align_current\|get_acpi_table_revision' -- src/) |grep "<" Change-Id: Icb90c70b0fb53175b9aaeabf067485a15fe71457 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-23ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki
Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/amd/bilby,mandolin: use full path of SoC's chip.hFelix Held
This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iba1948ae2332788b7e0ec9b4e3cea35c6608b152 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-20mb/amd/gardenia,padmelon;mb/google/kahlee: use full path of SoC's chip.hFelix Held
This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I10a18efb92ac0c3cad31044156e32aa6afe1d4d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-20mb/amd/gardenia,padmelon;mb/google/kahlee: add missing soc/gpio includesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie716633bd7602d5e4a7e186aa9e444b7f70dab56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-18amdfwtool: Call the set_efs_table for StoneyridgeZheng Bao
Related to https://review.coreboot.org/c/coreboot/+/58555 commit-id: 35b7e0a2d82ac In 58555, we added the SOC ID for Stoneyridge in amdfwtool command line. But it raised building error because it then called "set_efs_table" without setting SPI mode. So we skipped calling that. But in set_efs_table, it has case for Stoneyridge. The boards also need to have this setting. So we remove the skipping and give the proper SPI mode in mainboard Kconfig. Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-11ChromeOS: Replace with or add <types.h>Kyösti Mälkki
It's commented in <types.h> that it shall provide <commonlib/helpers.h>. Fix for ARRAY_SIZE() in bulk, followup works will reduce the number of other includes these files have. Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05mb/google,intel: Fix indirect include bootmode.hKyösti Mälkki
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-22AGESA binaryPI: Use common acpi_fill_madt()Kyösti Mälkki
Change-Id: I01ee0ba99eca6ad4c01848ab133166f8c922684d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-15mainboard: Drop invalid `VGA_BIOS_FILE` defaultsAngel Pons
If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig does not exist in the coreboot tree (including submodules), drop it. These files should be stored in the `site-local` subdirectory and the paths specified for each board in `site-local/Kconfig`. For example: config VGA_BIOS_FILE default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200 Note that this is just an example. There are better ways to structure one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option would be one of them, though variants may still need special handling. Also, update autoport to not generate `VGA_BIOS_FILE` defaults. Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-10-05src/mainboard to src/security: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-30mb/amd/bilby: Use I2S TDM interfaceAamir Bohra
Bilby uses I2S TDM interface for audio, instead of HDA interface. Change-Id: I7c8ec02d0e63730cb54a27d3bea1d102e037823d Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2021-09-23soc/amd: rename program_gpios to gpio_configure_padsFelix Held
Use the same function name as in soc/intel for this functionality. This also brings the function name more in line with the extended version of this function gpio_configure_pads_with_override which additionally supports passing a GPIO override configuration. This might cause some pain for out-of-tree boards, but at some point this should be made more consistent, so I don't see a too strong reason not to do this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-08mb/amd/{bilby,mandolin}: Turn empty `chip` entry into commentNico Huber
A chip entry in the devicetree is not hooked up without a device beneath it. It seems the intention was to leave these superio drivers unconfigured, so there should be no harm to turn the entries into comments. Change-Id: I6b606f35eba089b74c562084772d95be41cac39c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-08soc/amd/common/include/acpimmio: reduce visibility of GPIO MMIO accessFelix Held
Introduce amdblocks/acpimmio_legacy_gpio100.h so that the old pre-SoC chipsets can still access the raw GPIO100 and IOMUX ACPIMMIO registers while only allowing GPIO accesses through the GPIO API on the SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I18872dfa40d53ba8b0d7802eec52ede5e2ae617a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-30mb/(amd,google): Remove spi configuration from devicetreeMartin Roth
Now that the SPI configuration has been moved into Kconfig, it is no longer needed in devicetree. BUG=b:194919326 TEST=Build & boot guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ifdcd3f33173194c4a25794137756b143751edd70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/(amd,google): Update SPI Kconfig settings based on devicetreeMartin Roth
This takes the devicetree SPI settings and moves them into Kconfig. BUG=b:195943311 TEST=boot guybrush & majolica and verify spi settings. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Icce1d57761465ae8255e5d9ce8679f3fdcb0ceed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-27mb/amd/majolica/Kconfig: add EFS SPI settingsFelix Held
This keeps the default of EFS_SPI_SPEED at 66.66Mhz for the non-EM100 case, but switches the EFS_SPI_READ_MODE setting from Dual IO (1-1-2) to Quad IO (1-1-4) for the non-EM100 case. This patch adds a special config for the EM100 emulator case that has limited SPI frequency support. Tested on Majolica by Martin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8996c2bf606ccd21686092beac8d96b22c0b7869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56815 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-22AGESA f15tn: Factor out common OptionsIds.hAngel Pons
Subsequent commits will add Kconfig options to configure IDS. Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical. Change-Id: I861762280b274566ce14969a30e2e0c98e120a69 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-08-22AGESA f15tn: Drop `IDSOPT_ASSERT_ENABLED`Angel Pons
The `ASSERT` macro is already defined in `src/include/assert.h`, and AGESA's definition is never used. On Asus A88XM-E, toggling the value of the `IDSOPT_ASSERT_ENABLED` macro does not change the resulting binary when using reproducible builds. Attempting to use AGESA's definition of the `ASSERT` macro results in build errors: In file included from src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c:56: src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c: In function 'GetType4Type7Info': src/vendorcode/amd/agesa/f15tn/Include/Ids.h:371:33: error: statement with no effect [-Werror=unused-value] #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE)); Given that coreboot's definition of `ASSERT` is more useful, drop AGESA's broken definition and the useless `IDSOPT_ASSERT_ENABLED` macro. Also remove the `IdsAssert` function, as it is no longer used anywhere. Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical. Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-08-09mb/amd/bilby: Set Clk always on for x4 and x8 external PCIe SlotAamir Bohra
Keep the clock source for PCIe slots as always on. Also turn off the unused (0/1/5/6) clock sources. Currently bilby only uses clock sources 2, 3 and 4, out of which clock source 3 and 4 are routed for PCIe external slot. And clock source 2 is routed for M.2 PCIe slot. TEST:Verify end devices enumerate on D:F 1.1/1.2 RPs over warm reboot. Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Change-Id: Ida485b06279b0a8659c8d00873c3d6023d1e542f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56826 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05mb/amd/majolica:Enable IOMMU Device for majolicaJason Glenesk
Enable IOMMU PCIe device. BUG=b:194173037 TEST=lspci shows IOMMU device 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631 Cq-Depend: chrome-internal:4027293,4027294 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: Ia84276ca98163158d818a0efc3e021b93ab365de Reviewed-on: https://review.coreboot.org/c/coreboot/+/56771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-04mb/amd/bilby: Add support for HDMI displayAamir Bohra
DDI 0/1 ports are shared for DP and HDMI. This implementation adds support for HDMI display when HDMI is set as connector type in ddi descriptors. TEST=verify display over HDMI(0 and 1) in OS. Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Change-Id: I9697211c556f12d1fc0d49418b227fbe6b342673 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-04mb/amd/bilby: Enable DP2 and DP3 enumerationAamir Bohra
DP2 and DP2 is muxed with USBC port. This implementation configures mux for DP functioanlity. TEST=Verify display over DP2 and DP3. Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Change-Id: If0c8dfbb47175789bb27d4506c1e8b45c425c76a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-26mb/*: Specify type of `VARIANT_DIR` onceAngel Pons
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `FMDFILE` onceAngel Pons
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `DEVICETREE` onceAngel Pons
Specify the type of the `DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23soc/amd/stoneyridge/fch: change sb prefix of sb_clk_output_48Mhz to fchFelix Held
Stoneyridge has an integrated FCH and no south bridge, so change the sb prefix to fch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5154ae1158f864d4a2aca55e6bcce6a742c6afe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56527 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17soc/amd/picasso: introduce and use devicetree aliases for UART0-3Felix Held
Since the default state of the MMIO UART devices in the chipset devicetree is off, the mainboard devicetree entries that disable MMIO UART devices are removed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I913a587802020ce4e182b48632cdde1104c2a6e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55545 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07soc/amd/cezanne: Configure I2C Pad RX Select through devicetreeKarthikeyan Ramasubramanian
Some of the I2C buses are required to operate at different voltage level compared to other I2C buses eg. I2C bus to Google Security Chip (GSC) should be at 1.8V level. By default, all the I2C buses are initialized to operate at 3.3 V. Add support to configure I2C pad RX select through devicetree and update the concerned devicetree. BUG=b:188538373 TEST=Build and boot to OS in Guybrush. Ensure that the communication with GSC is fine. Build Majolica mainboard. Change-Id: I595a64736fdac0274abffb68c5e521302275b845 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-01mainboards using soc/amd/picasso: use aliases for remaining PCIe devicesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id2bdce5871f57e9edb17f89cba61b5c5ae018566 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01soc/amd/picasso: introduce and use chipset device treeFelix Held
The chipset devicetree only has the essential PCIe devices enabled that are needed for the SoC code to work. It also defines aliases for all PCIe devices that can be used to reference the devices in the mainboard- specific devicetrees and devicetree overrides. To make the change easier to review that part will be done in a follow-up patch. Despite missing in the PPR, device pci 18.7 exists on Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-28mb/amd/bilby,cereme,mandolin: change PSPP policy to balancedFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7571ed92b3c3fa79581e2c7342960ca31451af1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-27mb/amd/majolica: enable crypto coprocessor PCIe deviceFelix Held
This fixes the following error from the Linux kernel: ccp 0000:03:00.2: ioremap failed ccp 0000:03:00.2: initialization failed ccp: probe of 0000:03:00.2 failed with error -12 BUG=b:186575712,b:189202985 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id1c6a6cbbdda2cb22e81e2b52b364617d6765e09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54963 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27soc/amd/picasso: add devicetree setting for PSPP policyFelix Held
Since the default for the corresponding UPD of the Picasso FSP is DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE, add a deviectree setting for each board that's using the Picasso SoC code to not change the setting for the existing boards. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-27mb/amd/majolica: set PSPP policy to balancedFelix Held
BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5fd0021170777c755ecb78d339aec05ff786710f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54932 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14mb/amd/majolica: Disable IO ports 0x60/0x64Raul E Rangel
I suspect there is additional initialization required to enable the 8042 keyboard controller on the EC. By removing the range we no longer encounter long 20 second delays when reading the IO ports. Since depthcharge polls the IO ports it makes it seem like depthcharge locked up. BUG=b:182100027 TEST=Boot majolica with depthcharge to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I56a7eb4200e4615e1b4d9f14594d64f93e031a54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-10AGESA boards: Drop comments about `IDS_DEBUG_PORT`Angel Pons
No board defines this macro. In preparation to drop OptionsIds.h files from mainboards, remove commented-out references to `IDS_DEBUG_PORT`. Change-Id: I67a10d863aeea9e1b91c38aa02d19106b7b97659 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-05-10AGESA boards: Drop unused `IDSOPT_HOST_SIMNOW` macroAngel Pons
This macro is not used anywhere in AGESA. Remove all references. Change-Id: Ibc2876a5a8419ec4fa5a793bb996f5c14d989bac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-05-10AGESA boards: Drop unused `IDSOPT_HOST_HDT` macroAngel Pons
This macro is not used anywhere in AGESA. Remove all references. Change-Id: I9cd9fa0dc25b1143f8b4c1f20beffba638437398 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-05-10AGESA boards: Drop unused `IDSOPT_DEBUG_ENABLED` macroAngel Pons
This macro is not used anywhere in AGESA. Remove all references. Change-Id: Icae0ecae77a20e1568440e3191a29db33b5581d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-05-06soc/amd/common/espi,mb/: Allow configuring open drain ALERT#Raul E Rangel
Some designs might wish to use an open drain eSPI ALERT#. This change adds an enum that allows setting the eSPI alert mode. BUG=b:187122344, b:186135022 TEST=Boot guybrush using all 3 alert modes Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06mb/amd/majolica: Enable S0i3 by defaultJason Glenesk
Set s0ix_enable to true. BUG=b:178728116 TEST=Cold boot and perform a cycle of S0i3. Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: I808e78f41509cb03821513b5b63cc8856c891d8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-29soc/amd/common/acp: Move Audio Co-processor driver to commonKarthikeyan Ramasubramanian
Audio Co-processor driver is similar for both Picasso and Cezanne SoCs. Hence move it to the common location. BUG=None. TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards. Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-28mb/amd/majolica:Set IRQ for GPIO controllerJason Glenesk
AMD GPIO driver will not load if IRQ is not set. As a consequence, it does not clear the interrupt when waking from S0i3. BUG=178728116 TEST=Perform 2 S0i3 cycles, confirming second cycle does not return instantly due to first interrupt not being cleared. Change-Id: I3072263e8e68f939a47ed4125444c60133087824 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26mb/**/cmos.layout: Drop unreferenced `iommu` optionAngel Pons
No code in coreboot uses this option, so it might as well be dropped. Change-Id: Ie58bab7e87831db08b9f398a777ba350920b707b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52639 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26mainboard: Drop unreferenced CMOS optionsAngel Pons
Remove CMOS options that are not read anywhere in the code. They may have been used in the native AMD platform code, or got copied around from board to board and never did anything to begin with. Change-Id: Ib19ace4fa6e610a28e68fe2612b4e623f200f064 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52638 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-20mainboard: Drop redundant DEVICETREE configurationFelix Singer
`devicetree.cb` is the default value for the Kconfig DEVICETREE setting. Drop redundant configurations. Change-Id: I5eded3d5e38ca80986da2fda95050815c2702f82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52504 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19mb/amd/majolica: use GPIO_40 as reset pin for NVME SSDNikolai Vyssotski
Default Majolica configuration uses GPIO_40 for NVME M2_SSD_RST# BUG=b:182100027 TEST=ls /dev/nvme* Change-Id: Idecc0ec7eaf903b29fea109d3688f3c249da62f5 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-16soc/amd/cezanne: Add uart controllers to chipset.cbIvy Jian
Add uart controller to chipset.cb and leave it off by default. Turn uart0 on for console for mainboards. BUG=none TEST=builds and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Iaeb7fea4b92bd89331c7ae7c1c000f8d9961fe9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-12mb/amd/majolica/port_descriptor: use GPIO number defineFelix Held
TEST=Timeless build results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie39dc99bef4eb3776388d7406239bac6031bfaaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/52193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-12mb/amd/bilby: Use Picasso VBIOS as defaultRitul Guru
use PicassoGenericVbios.bin as default instead of raven VBIOS for Bilby. Change-Id: I99621173a33a1154f8bb4929d199288265bbe04d Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52209 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/amd/bilby: Enable postcode on port 0x80Ritul Guru
selecting SOC_AMD_COMMON_BLOCK_USE_ESPI will disable the lpc decodes, so not selecting that keeps the lpc decodes. Change-Id: I03a8d4b804cee205b9e06b00e2e5a442452f8f86 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52016 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/amd/bilby: enable boot from NVMe SSDRitul Guru
These changes involve NVMe specific GPIO programming to enable pcie NVMe SSD boot. Add nvme dev,func in devicetree and also remove unused GPIOs programmed in Bilby. Change-Id: I4407f82122c04b13684d4176ba5cd5a9fe03f0db Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51674 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/amd,google: use PAD_NF_SCI for GPIO_2 config in soc/amd based boardsFelix Held
When GPIO_2 was configured as PAD_NF with the WAKE_L function selected the GPIO_2 override in soc_gpio_hook called soc_route_sci that wrote the corresponding SCI mapping register, but didn't set up the SCI level and trigger type, so that couldn't have worked on most of the boards. The only boards where I think this was actually tested are the google/zork ones and they configured GPIO_2 as PAD_SCI where the GPIO mux setting is GPIO mode instead of the WAKE_L mode, but at least the SCI was configured correctly. The new PAD_NF_SCI macro can configure both the right GPIO mux setting and set up the SCI configuration correctly, so use this new macro for the GPIO_2 pin. For test purposes I also added the corresponding GPIO_2 configuration to amd/mandolin to see if the affected registers end up having the expected value using the HDT debugger to look at the registers, but didn't test the wake-up functionality, since S3 resume isn't working on amd/mandolin yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Ic069e46b759fb6746645faccd254263c49a892d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51756 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07mb/amd/majolica: add DXIO and DDI descriptorsFelix Held
TEST=Worked on Matt's Majolica board. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Change-Id: I65c7e0ebf1e43fd4608d46bae8a176cfc3d0236b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51956 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07mb/amd/majolica: add PCIe devices to devicetreeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I838aeda2e6c403eaa3388a6b934e7ab6b4e918e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSPMatt Papageorge
This patch adds the functionality to write the DXIO and DDI descriptors to the UPD data structure to the SoC code and adds the mainboard_get_dxio_ddi_descriptors function to each mainboard using the Cezanne SoC that gets called to get the descriptors from the board code. Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-29mb/amd: majolica,mandolin: Remove needless article from warningPaul Menzel
At the end of the built, the line below is printed. coreboot has been built without an the Microchip EC FW. Remove *an*, as one article is enough. Change-Id: I28b24f0f2dade17e30e16cc6d935976e331a7a97 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-25mb/amd/majolica: Enable IO port 2E/2FZheng Bao
MEC1701 can be accessed by IO port 2E/2F Change-Id: I31f1b147476ec487e64f3c30b3cf514b45ced416 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-22mb/amd/majolica: Set IOMUX to enable I2C2 & I2C3Zheng Bao
Change-Id: I142c06c150214d58acc04b8c6b3b027fff0256db Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-03-18mb/amd/majolica: Generate OIPG PackageRaul E Rangel
This fixes the unknown reference errors for OIPG. Since Majolica doesn't actually have any of the GPIOs ChromeOS uses, we leave the arrays empty. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifeae84e0ccab187a4e7131cd6ea9e1336d79df67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51536 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16AGESA,binaryPI boards: Drop invalid MP table filesKyösti Mälkki
If we spot any error in the file, treat it as untested and broken copy-paste. Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38313 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16AGESA,binaryPI boards: Move IRQ table programmingKyösti Mälkki
IRQ programming should be done outside (obsolete) MP table generation. Change-Id: Ibce2af4de91549c4c9743cd997f625164672a713 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38564 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/amd/majolica,google/guybrush,google/mancomb: select HAVE_ACPI_RESUMERaul E Rangel
Since not all mainboards based on the Cezanne SoC have to support ACPI resume, select this option in the mainboard's Kconfig and not in the SoC's Kconfig. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I988276ccb5b61837d7f3f015d1d1aba783324b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 08:32:36 +0000