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2015-03-07AGESA: Use same HeapManager for all BiosCallOutsKyösti Mälkki
We do not allow platforms to mess around with memory layout. Change-Id: I316ff522c8833fa3b7ad20f2c5a9cae21f4174d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8604 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-16mainboard/cmos: Kill off unused boot_* parametersTimothy Pearson
Change-Id: I19d6b56e3ac5e6e7946648b97c86a223b748e3bd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8460 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16mainboard/cmos: Move ECC variables out of fallback mechanism byteTimothy Pearson
Change-Id: Icebc12d8f83494150a7bdd3adcc168d7b48b2e68 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8458 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16mainboard/cmos: Delete obsolete commented parametersTimothy Pearson
Change-Id: Iccad79c142a7fcf89dd0fbebe8c07ad9ef019e91 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8459 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-01-10ACPI: Add acpi_is_wakeup_s3() for romstageKyösti Mälkki
This replaces acpi_is_wakeup_early(). Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8187 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06Remove AMD's "Release Content" doxygen from coreboot filesMartin Roth
These comments are left over and are not relevent in the coreboot code, but created a new section titled "Release Content" in the doxygen documentation produced by the coreboot code. In an effort to clean up the output, I'm removing these doxygen comments. Change-Id: I4d7be3313a2ab6c140b4f3afe70dffc4abba7bca Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8069 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06mainboard/*/romstage.c: Sanitize system header inclusionsEdward O'Callaghan
Fix system include paths to be consistent. Chipset support is part of the Coreboot 'system' and hence 'non-local' (i.e., in the same directory or context). One possible product of this, is to perhaps allow future work to do pre-compiled headers (PCH) on the buildbot for faster build times. However, this currently just makes mainboard's consistent. Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8085 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-04AMD Mainboards - PlatformGnbPcie.c: Fix Doxygen errorsMartin Roth
Remove PeiServices param for OemInitEarly - it doesn't exist in the function. Change-Id: I338aeb4128126f6e541815dc09bf8d23678081c8 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8073 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-20AGESA fam15tn fam15rl fam16kb: Add OemInitMid()Kyösti Mälkki
Change-Id: Icbad42168ec3afb7780c0c2ddc17aa405e08d693 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7825 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Add OemCustomize hooks structureKyösti Mälkki
We should potentially provide an OEM platform hook to manipulate parameters around any entry point to AGESA. Use structure for such ops to avoid weak functions and lots of empty function stubs. Change-Id: I99bf7de8a1e2f183399d2216520a45d0c24fd64c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7824 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Ignore error in OemCustomizeInitEarly()Kyösti Mälkki
It does not really matter if we continue or return after a failed assertion, system configuration is invalid anyway. Change-Id: I5ba47ee3fd6c5ff97b9229f8bfc9db08873b08ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7823 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Add amd_initcpuio() and amd_initmmio()Kyösti Mälkki
These are not wrappers for AGESA as they do not enter vendorcode at all. We expect most of the added fixme.c file to be written without use of AMDLIB.h and parts relocated as northbridge enable_resources(). Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7815 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19mainboard: Strip out some dead includesEdward O'Callaghan
Change-Id: I0079fa089ba863c6e447bcee3440a7e0ba0f2372 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7429 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA: Trace execution with AGESA_EVENTLOG()Kyösti Mälkki
Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7604 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA: Common agesawrapper for S3 resumeKyösti Mälkki
Change-Id: I27cd073331659e47d241a0ce249b2d080b4bab5c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7162 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA: Remove duplicate OemCustomizeInitEarly declarationsKyösti Mälkki
Change-Id: I59b2c3f235a6b30e68e78c2fe4065fbc0488bc4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7158 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA fam15tn / fam15rl / fam16kb: Common agesawrapperKyösti Mälkki
Split FCH parts to southbridge/hudson. Change-Id: Ibe305fc3e47422523a57ffa9cf69cd401c786ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7159 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial portKyösti Mälkki
Move LPC decode enable out of agesawrapper.c. It should not be on the execution path of AP CPUs and function is not related to AGESA per se. Change-Id: I19d6a20fbc7a3d28601caa9aaa1d73d6930257ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7602 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA: Report events with AGESA_EVENTLOG()Kyösti Mälkki
NOTE: For fam12 and fam14 ASSERT() is defined empty so execution may fall through critical failures. Change-Id: Ifef65d749d340f1df3a43b5fcb38c4315ef944e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7154 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA: Use common header for agesawrapperKyösti Mälkki
Change-Id: I5189d0c55635aeb29553fd04a67490cfee3d88d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7153 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA Hudson/Yangtze: Remove unused GPP configuration in devicetreeKyösti Mälkki
GPP config from devicetree.cb is not implemented for fam15tn/fam16kb. Also only for asus/f2a85-m the configuration value matched the actual programming. Change-Id: Ic7a9aa1360f4ba35d202f3f7dd1fc3c20a52dde0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7600 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA Hudson/Yangtze: Remove obsolete devicetree parametersKyösti Mälkki
Change-Id: Ic6affae7e508f28b131c7d07191289f4fcbf2d74 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7599 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-26agesa/family15tn: Switch to per-device ACPIVladimir Serbinenko
Change-Id: Icc2e7b66b3ff5f70b219a3e67494ce3df055c9d5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7033 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-14AMD: Move RAMBASE and RAMTOPKyösti Mälkki
There are no reasons to not load ramstage @ 0x100000. Boards with HAVE_ACPI_RESUME enabled have performance penalty in using excessive RAMTOP. For these boards, this change releases 11 MiB of RAM from CBMEM allocation to OS. Change-Id: Ib71995aba5e9332d0ec1626b3eb3b4ef6a506d1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7094 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-07mainboard: Trivial - Make AGESA board include consistentEdward O'Callaghan
Change-Id: If6cb99469f56fff8f88b294b625f0a5205ec540b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7238 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-03AMD boards: constify romstage variablesPatrick Georgi
That takes them out of .data Change-Id: Idf88ddaacb2f78ba6a0260e3511b34edc269731d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7313 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-10-22AGESA fam15tn fam16kb: Fix missing FCH function prototypesKyösti Mälkki
Change-Id: I242664032d368794d828fce73a20f75ded45051d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7151 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-10-22AGESA boards: Fix early agesawrapper_amdinitmmio()Kyösti Mälkki
Regression introduced with commit 7b23ae0 AGESA: Trace execution with AGESAWRAPPER() As the call is made before console_init() is called it must not call any printk(). Debugging Olivehill and Parmer platforms using a custom FPGA (as these boards have no Super-IO UART) have been observed to halt and/or delay at early boot. Change-Id: I3ab4e5378db44aece9046c8636cde1053ce5390d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7059 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
2014-10-19AGESA: Drop board and chipset -specific callout headersKyösti Mälkki
Change-Id: If973f28931e65a57cbb8d6739542a57c844f0d66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7115 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-19AGESA fam15tn fam16kb 00730f01: Add common agesa_readSpd()Kyösti Mälkki
Remove northbridge specific callouts for AGESA_READ_SPD. Move low-level SMBus code to southbridge. Change-Id: I3e272389e2a7db542fb48fca8606325af27b65a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7112 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-19AGESA: Declare callout Fch_Oem_config staticKyösti Mälkki
Change-Id: If5c62b868c4144845d79dc26068c500ab5d26947 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7111 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA boards: Drop get_bus_conf.c filesKyösti Mälkki
The only remaining purpose for get_bus_conf() was to fill in obscure bus_sb800 (etc.) arrays containing partial PCI bus enumeration. Complete enumeration is available in devicetree and PCI configuration space so discard these arrays. Change-Id: I733115940afba3a50c58aedb9a04ecf5082b1234 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6360 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA f14 f15tn 16kb: Move IOAPIC ID setup out of get_bus_conf()Kyösti Mälkki
Change-Id: I7fd14c17242cd3deb7a784fc918ad6fe1191bd13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6359 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA boards: Use devicetree for PCI bus enumerationKyösti Mälkki
Previously MP table contained PCI_INT entries for PCI bus behind bridge 0:14.4 even if said PCI bridge function was disabled. Remove these as invalid, indeterminate bus number could cause conflicts. PCI_INT entries with bus_sb800[2], bus_hudson[2] and bus_yangtze[2] were invalid as there is no PCI bridge hardware on device 0:14.0. Remove these as invalid, indeterminate bus number could cause conflicts. Change-Id: Ie6a3807f64c8651cf9f732612e1aa7f376a3134f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6358 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA: Drop some excessive agesawrapper.h includesKyösti Mälkki
Change-Id: I3807912b1dc68fae8248a66e37bbe642fb92d3ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6262 Tested-by: build bot (Jenkins)
2014-07-25AGESA f15tn f16kb: Fix HUDSON_XHCI_ENABLEKyösti Mälkki
Control for XHCI was split to handle AMD_INIT_RESET in agesawrapper while AMD_INIT_ENV was already handled as part of BiosCallouts. OEM configuration is supposed to be implemented as part of BiosCallouts, leaving agesawrapper agnostic of platform details. TODO: S3 resume for XHCI1. Change-Id: Id5e9c25a227db4d821f1be4b176470547ca4ea84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6241 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-07-24AGESA hudson yangtze: Move IMC firmware init out of get_bus_conf()Kyösti Mälkki
Change-Id: I5b3cbc4d25f06a5f916760d4474621abbf826ee4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6355 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24AGESA: Drop offset on PCI device enumerationKyösti Mälkki
Integrated PCI devices in southbridge silicon have static BDFs, no need to have variables to store the parent bus or an offset with constant zero. Change-Id: I37d3794d36b5e5775da9215574ddc199696646d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6333 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24AGESA: Drop unused extern declarationsKyösti Mälkki
Change-Id: I7f681b40251f49ff717589ed5e7d7e00ee36c7c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6332 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24AGESA boards: Drop global bus_isaKyösti Mälkki
Only ever used as lvalue (except when incrementing) so this global is unused. Change-Id: I616721f937eb0bfdb28f356284efd70f99ccd2dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6330 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24src/mainboard: Remove trailing whitespaceElyes HAOUAS
Change-Id: I14a9dc99acb5d5365a3d7e99a3964120bb611b05 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6308 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-18mainboard: Make use of ARRAY_SIZE in buildOpts.c on AGESA platformsEdward O'Callaghan
Found using coccinelle. Change-Id: I406de6cfe25d3b471dbb6f98d9c62addae008de3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6195 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-17AMD get_bus_conf(): Drop bus_type arrayKyösti Mälkki
Only ever used as lvalue, so no point creating the array. Change-Id: I6699dfae9377a895e9bc4a52579d00ddcfa60a9f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6277 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-07-17mainboard,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: Ib531a54db7df6b49a6218f689dcaab712e9dfb01 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6292 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-14AGESA boards: Use IS_ENABLED() for HUDSON_LEGACY_FREEKyösti Mälkki
Change-Id: Ib2a015dac82cec8538f8b1a1c2d45b20b05747bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6239 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-07-14AGESA: Trace execution with AGESAWRAPPER()Kyösti Mälkki
Implement logging just once to have uniform output. Change-Id: I8db694a3bf6b1af459bdf98f7acb99edf4dd07f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6180 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AGESA: Fix error status code return type to enum from UINT32Edward O'Callaghan
AGESA correctly uses the enum AGESA_STATUS type whereas boards use a mess of UINT32 typecasts. Also no need to shout VOID. We are not that careful on changing all cases of VOID->void or whitespace issues as these files will get merged with follow-ups. Change-Id: I16ccfcc73cda6b917c7ff5fd42ee2cd04e7dc0dd Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6182 Tested-by: build bot (Jenkins)
2014-07-03AGESA boards: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: Ib76ec433710b3a7c26360329a9403585d6f4fe4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6143 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03AGESA: Call get_bus_conf() just onceKyösti Mälkki
Instead of calling get_bus_conf() three times from write_tables() and executing it once, just make one call before entering write_tables(). Change-Id: I818e37128cb0fb5eaded3c1e00b6b146c1267647 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6133 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03AGESA: Add agesawrapper_post_device()Kyösti Mälkki
NOTE: The procedure is moved across a collected timestamp TS_WRITE_TABLES, so the delay of SPI erase/write will be accounted for in an earlier entry in cbmem -t output. Change-Id: I0f082e7af1769c8d7d03cdd51fdb5dacbf3402b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6132 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03AGESA boards: Use acpi_s3_resume_allowed()Kyösti Mälkki
This adds use of BROKEN_CAR_MIGRATE to include CBMEM symbols for the build of romstage also for boards without HAVE_ACPI_RESUME. These symbols got exposed as the use of preprocessor directives was reduced. We expect the linker to do a fair job and optimize away function bodies that are on unreachable execution paths. Change-Id: Ibf5181d3eecb87ce647abe0be01072594b05aa5f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6067 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03AGESA boards: Add prepare_for_resume()Kyösti Mälkki
Use one common implementation for all AGESA platforms. Change-Id: I410f8e0a9c75445882d67659cde00004eb7ad6b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6084 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-26AMD boards: Fix typosKyösti Mälkki
Change-Id: I92f3877b58d9acaa9578337e66107e9cd9f46043 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6110 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26PIRQ tables: Fix typosKyösti Mälkki
Change-Id: I4d8abe3841378e06515e1b3a8f22d78425d08449 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6109 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-25Declare acpi_is_wakeup_early() only onceKyösti Mälkki
Change-Id: I5314d76168c40a6327d4a9ac3b4f4fb05497d6fc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4525 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-14amd/agesa,cimx: Rename ACPI OS detection methodsEdward O'Callaghan
Try to 'standardize' the otherwise peculiar method naming to be somewhat more in-line with other ACPI implementations. This makes it easier to compare with vendor DSDT dumps for example. Change-Id: I5ba54f7361796669ac0cab7ff91e7de43b22e846 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5888 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-14mainboard/amd: De-ASCIIartify reference boardsEdward O'Callaghan
For anyone who knows the difference between a header and a variable in C these depictions are rather useless. Thus, these lines wast essential screen real estate while working on coreboot. Change-Id: I7fe55d936c035ef83832716c45bfc57d73c0edc7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5979 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-13mainboard.c: Fix typo in appro*p*riate in commentPaul Menzel
Use the following command to fix all occurences. $ git grep -l approriate | xargs sed -i 's/approriate/appropriate/g' Change-Id: I4cbba972bb445c2407ef2e63ffb3068fc948f1c6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5987 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-06AGESA: Use common heap allocatorKyösti Mälkki
Change-Id: I5df1f0efdef2592b762fe391edaadbca4593e85a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5689 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-06AGESA: Use common GetBiosCallout()Kyösti Mälkki
Change-Id: I9c8f7cc98c65102486e17ec49fa2246211dffc4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5688 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-06AGESA fam15tn fam16kb: Use shared default calloutsKyösti Mälkki
Change-Id: Ibbb07ef308c7e92a8a8dfe066f5e3866d5f8aee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5687 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-06AGESA fam15tn fam16kb: Use common handler for GNB_GFX_GET_VBIOS_IMAGEKyösti Mälkki
Change-Id: I158993bcb654ef27a9fc6b7e9dc3fc955fb740fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5686 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26AGESA: Add common calloutsKyösti Mälkki
Most of the callouts are not specific to board or even family. Start new file with default callouts doing nothing and returning either AGESA_SUCCESS or AGESA_UNSUPPORTED. Also add callout for returning empty IdsIdData. This feature is not used and could be easily overriden at board-level at later time. Change-Id: I65dbcdd80dddc89d47669ebe62c22caa63792f5c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5678 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-13southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridgeEdward O'Callaghan
We should configure i8254/i8259 down in to the southbridge rather than romstage of every AGESA/CIMx board much like Intel boards do. Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5669 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10Replace SERIAL_CPU_INIT with PARALLEL_CPU_INITKyösti Mälkki
Lines with 'select SERIAL_CPU_INIT' where redundant with the default being yes. Since there is no 'unselect SERIAL_CPU_INIT' possibility, invert the default and rename option. This squelches Kconfig warnings about unmet dependencies. Change-Id: Iae546c56006278489ebae10f2daa627af48abe94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5700 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-05AGESA: Implement EmptyHeap()Kyösti Mälkki
Heap allocation begins with BIOS_HEAP_MANAGER, no need to clear the fields individually. Change-Id: Ia1af84bd09d1edf8f72223752557d44a96dec6e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5659 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15tn: Use common GetHeapBase()Kyösti Mälkki
Implementation of this function is common for all boards in family, and also across different families. Change-Id: I562a132fa6d3ade2700d9a375d7aa21fcf8ea890 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5653 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
CONFIG_ARCH is a property of the cpu or soc rather than a property of the board. Hence, move ARCH_* from every single board to respective cpu or soc Kconfigs. Also update abuild to ignore ARCH_ from mainboards. Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5570 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28AMD: Add common header file for CAR setupKyösti Mälkki
Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4683 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-26mainboard/*: Remove DUMP_ACPI_TABLES from amd boardsEdward O'Callaghan
Dumping the ACPI tables in this way has limited use, is not likely to be used and is poorly implemented. There are much more sophisticated tools available on Linux for debugging ACPI as such this code is outside the scope of coreboots 'bring up the hardware only' philosophy. A more generic implemention could be done with hexdump() in coreboot proper following on from this cleanup. Change-Id: Ifd3bfb76338609d18fcf7158d3c9a6d7c06c8847 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5530 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-21AMD hudson and yangtze boards: Let mainboard declare power buttonAlexandru Gagniuc
The power button was declared by hudson's ASL as \_SB.PCI0.PWRB, and always had the wake source declared as GPE3. This is not the correct wake source for all boards. On some laptops declaring a wake source is not needed, as the wake mechanism is handled by the EC. Move the declaration of the power button to mainboard ASL files, and scope it as \_SB.PWRB . This also makes the naming consistent with the examples in the ACPI spec. The wake source for the PWRB of HP Pavilion M6 1035dx is removed, as it is incorrect. Change-Id: I9c76566025e7f200c0376673f6c6ea299afa4a5d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5546 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-17AMD hudson yangtze: Drop MAX_PHYSICAL_CPUS in commentsKyösti Mälkki
Change-Id: I81de291da7b3db8d04a127d5a304b558f1c75b34 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5535 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-16southbridge/hudson: Use MMIO instead of PIO to access PM spaceAlexandru Gagniuc
The MMIO region is set up by AGESA very early on, so we can use it to access the PM register space in ramstage. 16-bit accessors are also provided to simplify some setup tasks. 16-bit accesses are not possible via PIO. The pm2_iowrite/read accessors are removed, as they are not used. Change-Id: Ie7967b5086eb004525c39721338c6495aedc8165 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5503 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-16AMD hudson yantgze: Drop MAX_PHYSICAL_CPUSKyösti Mälkki
Not used with AGESA vendorcode. Change-Id: I4de7e49d513a1bc8d6d4da1eea630b9eedf5de80 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5522 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-04-16AMD hudson yantgze: Drop APIC_ID_OFFSETKyösti Mälkki
Not used with AGESA vendorcode. Change-Id: I1c4e1dea8836143334d336f99afcee2ca326b0c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5521 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-04-16AMD AGESA: Drop SB_HT_CHAIN_UNITID_OFFSET_ONLYKyösti Mälkki
Not used with AGESA vendorcode. Change-Id: Ic9a0513641bf76d748bb106675bccc33c7abe21e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5520 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-16AMD AGESA: Drop LIFT_BSP_APIC_IDKyösti Mälkki
Not used with AGESA vendorcode. Change-Id: Ie99abf5bcffd740e2e7ed6d78937ab32935ef214 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5519 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-04-16AMD AGESA: Drop AMDMCTKyösti Mälkki
This config option is fam10 only. Change-Id: I7f4619d2d4e7e7695a8ee691d879df2748f1c0c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5518 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-16AMD Thatcher: add IMC fan controlWANG Siyuan
There are 3 steps to enable the IMC fan control: 1. Enable fan control related registers on Hudson using oem_fan_control(). 2. Set EcStruct. 3. Enable thermal zone using enable_imc_thermal_zone(). I have tested on Thatcher. Change-Id: I959721b4fd8787ac0824f9f873efd4788682eedb Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/5359 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-13hudson boards: Don't require ide.asl file on boards without IDEAlexandru Gagniuc
Not all boards which use the AMD Hudson southbridge have IDE. However, the southbridge's asl included an 'ide.asl' file which had to be present in $(mainboard_dir)/acpi. Address this issue by removing the inclusion of 'ide.asl' from the southbridge 'fch.asl' and remove 'ide.asl' from Hudson boards, none of which have IDE. If future hudosn board will come with IDE, the device can be declared in the PCIO scope of dsdt.asl, right below the inclusion of 'fch.asl'. Change-Id: Ie2efb7ebf8f5b527e26d7aaaeafbd3053a9a6b28 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5459 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-19board-status: Add board_info.txt extracted from wiki.Vladimir Serbinenko
board_info.txt is a file to be used by board-status to add some useful info to the generated table like flash chip type. This series is autogenerated from wiki page Supported_Motherboards. Change-Id: Ie2bda900713ef4883134477163320936c84c34f5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4701 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-15Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki
This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be set with values that are not power of 2. The region programmed as WB cacheable will include all of ROM_SIZE. Side-effects to consider: Memory region below flash may be tagged WRPROT cacheable. As an example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB. Since this can overlap CAR, we add an explicit test and fail on compile should this happen. To work around this problem, one needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and define a smaller region for WB cache. With this change flash regions outside CBFS are also tagged WRPROT cacheable. This covers IFD and ME and sections ChromeOS may use. Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4625 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2013-12-26AMD AGESA: Drop MEM_TRAIN_SEQKyösti Mälkki
This config was for AMD K8 only. Change-Id: Ic1ce60041fef6ddee2dae0e3559fb78f088740af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4556 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-11-22AMD f15tn, f16kb: Remove CDIT table and DMI tableWANG Siyuan
On AMD Trinity and Kabini boards errors similar to the following are shown. ASSERTION FAILED: file 'src/mainboard/asrock/imb-a180/agesawrapper.c',line 431 DmiTable:100123f7, AcpiPstatein: 10010129,AcpiSrat:0,AcpiSlit:0, Mce:10010de9,Cmc:10010eab,Alib:1002111c, AcpiIvrs:0 in agesawrapper_amdinitlate agesawrapper_amdinitlate failed: 5 The reason is that on f16kb boards, the CDIT and DMI table are not created. On f15tn boards, only the DMI table is not created. Until the root cause is found, disable the table generation to remove the errors. Thanks to Wei Hu for debugging and reporting this issue on the list [1]. [1] http://www.coreboot.org/pipermail/coreboot/2013-November/076607.html CDIT table is not created Change-Id: I837e3c322bb5331a9b950a72397796a60642c3f3 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/4092 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-11-12AMD Hudson: Move function s3_resume_init_data to southbridgeZheng Bao
Besides the AGESA static settings, the settings in mainboard/buildOpt.c also change the final configuration. We need to make sure the settings in FchParam in resume stage are the same as they were in cold boot stage, otherwise the board can not wake up more than once. Tested on AMD/Olive Hill, AMD/Parmer and ASRock/imb-a180. (USB keyboard doesn't work when board wakes up. It is not introduced by this patch. It needs more debugging.) Change-Id: I5a5e5502080e358ffc3577dc6a40bb762844d998 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/3932 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2013-10-07AMD hudson yangtze: Fix corruption of a global ramstage variableKyösti Mälkki
A late for loop may reference over the current array allocation and corrupt an unrelated global variable. As a quick fix bumb the size of the array allocation uniformly to 6. We missed these boards for commit 9c7d73ca because the arrays had been renamed. Change-Id: Iff2f2a0090d9302576bc72195d2a3f6fa37ce29a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3954 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-08-15Include boot_cpu.c for romstage buildsKyösti Mälkki
ROMCC boards were left unmodified. Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15AMD Fam15tn boards: BiosCallOuts.c: Remove board name from `CodecTableList`Paul Menzel
The board name in that variable name is not necessary, as it is not board dependent, that means using the file as a template for making a new coreboot port for another motherboard the variable does not need to be changed, and just increases the code differences between AMD Parmer, AMD Thather and ASUS F2A85-M. So use a generic name. The same was done for AMD Persimmon (and inherited by the LiPPERT FrontRunner/Toucan-AF) in the following commit. commit 5e70766f14253f53190ddd49a544460c6bc1e528 Author: Jens Rottmann <JRottmann@LiPPERTembedded.de> Date: Tue Feb 26 15:56:11 2013 +0100 AMD Fam14 boards: reduce unnecessary differences, 2nd attempt Reviewed-on: http://review.coreboot.org/2529 The board name is *not* removed from the `CODEC_ENTRY` variable name as the verb table not only depends on the codec but also on the board [1]. Having the board name in the variable name is a good indicator that the pin configuration needs to be adapted when taking this file as a template for a new port. If it was board independent, a default chip configuration could be used and shared between all boards, which is unfortunately not the case. [1] Unfortunately I was not able to find Jens’ comment in my mail archive and in the Gerrit Web interface. Not sure where it is, but I am sure he made that comment. Change-Id: I440a306cf4ff0a5b1b61d1983d70c66d129904d0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3199 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-08AMD Thatcher: Split DSDT into common sections (as per Parmer)Kimarie Hoot
Rearranged the Thatcher DSDT file to match the functionality found on Parmer. As with the Parmer implementation, the Thatcher dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. As with Parmer, some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for Thatcher. Change-Id: Ie44a32959cc547840914365e872416d4624d33df Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/3804 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-07-10Rename hardwaremain() to main()Stefan Reinauer
... and drop the wrapper on ARMv7 Change-Id: If3ffe953cee9e61d4dcbb38f4e5e2ca74b628ccc Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3639 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-24AMD: Drop empty root_complexKyösti Mälkki
There are no files to build left under AMD nortbridge/x/root_complex directories. For some cases, even the Kconfig file was no longer sourced. Remove all such references and empty files. For devicetree.cb treat component paths with "/root_complex" in them valid even when the directory does not exists. This is because AMD boards us this dummy chip component as the root node in their devicetree.cb. The generated devicetree file static.c remains unchanged. Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3434 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-23AMD boards: routing.asl: Uniformly start `Package()` with capital letterPaul Menzel
In commit Rudolf Marek discovered, that it is not uniformly written. As »ASL names are not case-sensitive and will be converted to upper case.« [2] this change does not have any functional change. The following command was used to create this patch. $ git grep -l 'package()' src/mainboard | xargs sed -i 's,package(),Package(),' [1] http://review.coreboot.org/#/c/3318/ [2] http://www.acpi.info/spec40a.htm (18.2.1 ASL Names) Change-Id: I1784dbc50936a1ef9d4376209a3c324ef1fb85cf Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3516 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17AMD southbridges: Move HAVE_HARD_RESETKyösti Mälkki
All 3 boards with AGESA_HUDSON had HAVE_HARD_RESET with the reset.c file already placed under southbridge/. All 15 boards with CIMX_SBx00 had HAVE_HARD_RESET with functionally identical reset.c file under mainboard/. Move those files under respective southbridge/. Change-Id: Icfda51527ee62e578067a7fc9dcf60bc9860b269 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3486 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17Add support for XHCI (USB 3.0)Dave Frodin
CONFIG_HUDSON_XHCI_ENABLE will control the XHCI flags in the amd/parmer and asus/f2a85-m mainboards. The XHCI ports on amd/thatcher are not wired to USB jacks so always disable the flags. This was tested on amd/parmer using a USB 3.0 thumbdrive. Change-Id: I596b040fec30882d8d4dee34ab9f866dc1f8896b Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/3465 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13AMD Thatcher: fix issue 'S3 fails to suspend after wake up from USB keyboard'Siyuan Wang
This issue can be reproduced in Linux by the following steps: 1) use pm-suspend to suspend. 2) use USB keyboard to wake up. 3) use pm-suspend to suspend. FAIL To SUSPEND. The cause of this issue is: USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event, but this bit is not clear after wake up. So OS thinks there is a wake up signal and wake up immediately. In this patch, I add AcpiGpe0Blk using MMIO access and write 1 on bit 11. Write 1 to clear as spec says. I have tested on Thatcher The same change was done for AMD Parmer in commit »AMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard' (03901124) [1]. [1] http://review.coreboot.org/#/c/3347/ (Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1) Change-Id: Iaef39237497ef896d0f186e8f5522222c0ce6cb7 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3374 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-31AMD Trinity boards: Add reserved memory area for SPI base address in ACPISteven Sherk
- SPI controller base address gets overwritten by SD controller under Linux. - Reason for overwrite is the SPI base address isn't in a standard BAR and doesn't get automatically reserved. Solution is to add it as a reserved memory area in ACPI. - This issue was found on the ASUS F2A85-M platform. Currently a workaround on this platform was made as part of: http://review.coreboot.org/#/c/3167/3 - Once approved a follow-on patch for other southbridges using a non-standard BAR for the spi controller. Change-Id: I1b67da3045729a6754e245141cd83c5b3cc9009e Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/3270 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-30AMD Trinity boards: Use `sizeof(var)` to get its sizeRudolf Marek
Change `sizeof(type) * n`, where n is the number of array elements, to `sizeof(variable)` to directly get the size of the variable (struct, array). Determining the size by counting array elements is error prone and unnecessary. Not sure why the copy is needed instead of direct reference. Maybe it has something to do with CAR? These changes are based on Rudolf’s original patch »ASUS F2A85-M: Correct and clean up PCIe config« [1], where it was just done for the ASUS board. [1] http://review.coreboot.org/#/c/3194/ Change-Id: I4aa4c6cde5a27b7f335a71afc21d1603f2ae814b Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3247 Tested-by: build bot (Jenkins) Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-14AMD Fam15tn boards: BiosCallOuts.c: Declare codec arrays as `static`Paul Menzel
These arrays are declared as `static` for AMD SB800 based boards, so do the same for this generation. Rudolf Marek just changed `const CODEC_TBL_LIST` to `static const` in [1]. Adapt all Fam15tn based boards (AMD Parmer, AMD Thatcher, ASUS F2A85-M) to keep the differences between them small. [1] http://review.coreboot.org/#/c/3170/3/src/mainboard/asus/f2a85-m/BiosCallOuts.c Change-Id: I353b38bd8bc77ba500a4b7fe9250e9aa3071c530 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3198 Tested-by: build bot (Jenkins)
2013-05-14AMD Fam15tn boards: Document lane ID mapping from BKDGRudolf Marek
To make it easier to fill in the values, place the table from the BIOS and Kernel Developer’s Guide (BKDG) [1] as a comment. [1] http://www.coreboot.org/Datasheets#AMD_Fam15 Change-Id: I218f76e9fa2dc88d47af51ea6c062e315afb0000 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3221 Tested-by: build bot (Jenkins)
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