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2006-04-03comment out reset in MB ConfigYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-02issue 41 - fix up motherboard compilation. There's always hope.Stefan Reinauer
1201_ht_bus0_dev0_fidvid_mb.diff part 1 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-25- See Issue Tracker id-13 "lnxi-patch-13".Jason Schildt
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-25- See Issue Tracker id-12 "lnxi-patch-12".Jason Schildt
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-08eric patchYinghai Lu
1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-61arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> write_pirq_routing_table for x86 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-34arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-24arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> AMD MB IDE enable in Config.lb git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1940 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-10nodeidYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05- Ensure every copy of Options.lb uses:Eric Biederman
CROSS_COMPILE CC HOSTCC OBJCOPY git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05- Modify all of the Opteron motherboards to have a separate logicalEric Biederman
chip for the amdk8/root_complex git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04- Update abuild.sh so it will rebuild successfull buildsEric Biederman
- Move pci_set_method out of hardwaremain.c - Re-add debugging name field but only include the CONFIG_CHIP_NAME is enabled. All instances are now wrapped in CHIP_NAME - Many minor cleanups so most ports build. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21adapt config filesStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21update failover handling of some amd64 boardsStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21- Bump the LinuxBIOS major versionEric Biederman
- Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- First stab at running linuxbios without the old static device tree.Eric Biederman
Things are close but not quite there yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-08move default_resource_map to its own fileLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-15add support for AMD Serenade mainboard, why we have phantom devices here?Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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