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Change-Id: I3807912b1dc68fae8248a66e37bbe642fb92d3ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6262
Tested-by: build bot (Jenkins)
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Control for XHCI was split to handle AMD_INIT_RESET in agesawrapper
while AMD_INIT_ENV was already handled as part of BiosCallouts.
OEM configuration is supposed to be implemented as part of BiosCallouts,
leaving agesawrapper agnostic of platform details.
TODO: S3 resume for XHCI1.
Change-Id: Id5e9c25a227db4d821f1be4b176470547ca4ea84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6241
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
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Like many other (but not all) BiosCallouts, StdHeader is also passed
as ConfigPtr argument. Use that instead to make no assumptions of the
real type of FchData as it changes depending of the StdHeader.
Change-Id: Ibdf01d08e63b9e1b8e99ac16abb7f807d37a056e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6240
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: Ib2a015dac82cec8538f8b1a1c2d45b20b05747bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6239
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Martin Roth <gaumless@gmail.com>
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Change-Id: I5df1f0efdef2592b762fe391edaadbca4593e85a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5689
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: I9c8f7cc98c65102486e17ec49fa2246211dffc4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5688
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: Ibbb07ef308c7e92a8a8dfe066f5e3866d5f8aee2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5687
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: I158993bcb654ef27a9fc6b7e9dc3fc955fb740fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5686
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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There are 3 steps to enable the IMC fan control:
1. Enable fan control related registers on Hudson using oem_fan_control().
2. Set EcStruct.
3. Enable thermal zone using enable_imc_thermal_zone().
I have tested on Parmer.
Change-Id: Id11d5c5da30346c034d155a73749e7f4c9c980eb
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/4302
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
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The board name in that variable name is not necessary, as it is not board
dependent, that means using the file as a template for making a new
coreboot port for another motherboard the variable does not need to be
changed, and just increases the code differences between AMD Parmer,
AMD Thather and ASUS F2A85-M. So use a generic name.
The same was done for AMD Persimmon (and inherited by the LiPPERT
FrontRunner/Toucan-AF) in the following commit.
commit 5e70766f14253f53190ddd49a544460c6bc1e528
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date: Tue Feb 26 15:56:11 2013 +0100
AMD Fam14 boards: reduce unnecessary differences, 2nd attempt
Reviewed-on: http://review.coreboot.org/2529
The board name is *not* removed from the `CODEC_ENTRY` variable name as
the verb table not only depends on the codec but also on the board [1].
Having the board name in the variable name is a good indicator that the
pin configuration needs to be adapted when taking this file as a template
for a new port. If it was board independent, a default chip configuration
could be used and shared between all boards, which is unfortunately not
the case.
[1] Unfortunately I was not able to find Jens’ comment in my mail archive
and in the Gerrit Web interface. Not sure where it is, but I am sure
he made that comment.
Change-Id: I440a306cf4ff0a5b1b61d1983d70c66d129904d0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3199
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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CONFIG_HUDSON_XHCI_ENABLE will control the XHCI flags in the
amd/parmer and asus/f2a85-m mainboards. The XHCI ports on
amd/thatcher are not wired to USB jacks so always disable the flags.
This was tested on amd/parmer using a USB 3.0 thumbdrive.
Change-Id: I596b040fec30882d8d4dee34ab9f866dc1f8896b
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3465
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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These arrays are declared as `static` for AMD SB800 based boards,
so do the same for this generation.
Rudolf Marek just changed `const CODEC_TBL_LIST` to `static const`
in [1]. Adapt all Fam15tn based boards (AMD Parmer, AMD Thatcher,
ASUS F2A85-M) to keep the differences between them small.
[1] http://review.coreboot.org/#/c/3170/3/src/mainboard/asus/f2a85-m/BiosCallOuts.c
Change-Id: I353b38bd8bc77ba500a4b7fe9250e9aa3071c530
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3198
Tested-by: build bot (Jenkins)
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The "gigabit ethernet controller" (GEC) block was added to AMD
Hudson A55E to integrate ethernet capabilities into an AMD
southbridge.
The GEC is designed to work with B50610 and B50610M gigabit PHY
chips from Broadcom. These parts may not be generally available
in small quantities for embedded development.
The GEC block requires an opaque firmware blob to function. The
GEC blob is controlled by AMD and Broadcom and is not available
from coreboot.org.
This change removes GEC support from AMD Parmer and AMD Thatcher
mainboards since these boards do not have the Broadcom PHY.
AMD has requested that the GEC be hidden for Hudson FCH since
the PHY parts are not generally available. This Kconfig option
can make it appear that this is a viable and supported way to
add Ethernet to an embedded board. It is possible to use the
Hudson GEC block with other PHYs, but this requires development
of a custom GEC blob and a custom Ethernet driver. A custom GEC
blob has been developed for a Micrel PHY, but there is no
accompanying driver.
Change-Id: I7a7bf4d41e453390ecf987c9c45ef2434fc1f1a3
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3127
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
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In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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Continuing with the mainboard cleanup for F15tn, move the functions
to read the SPD from the mainboards for Thatcher and Parmer into the
wrapper for the northbridge/amd/agesa/family15tn.
Move the SPD address customization for the mainboard into the
devicetree.cb file.
Unrelated side note - Porting.h has an un-closed #pragma pack(1)
that can cause confusing side-effects. AGESA's structures all
use this, but coreboot's don't. Be sure to include the coreboot
.h files BEFORE Porting.h is included, not after.
This fix has been tested.
Change-Id: I89cdd225be61f60c6b8e7020e6f8b879983bbd96
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2190
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
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There are currently too many things in the mainboard directories that
are really more suited to being in the northbridge / southbridge
wrappers. This is a start at moving some of those functions down
into the wrappers.
Move the bios callback functions into the northbridge/amd/agesa/family15tn
directory from the mainboard directories. These can still be overridden
by any mainboard just by updating the pointer in the callback table to
point to a customized version of the function.
Change-Id: Icefaa014f4a4abbe51870aee7aa2fa1164e324c1
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2169
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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Add Kconfig option for Legacy free and hook it into the parmer
AGESA initialization as well as the FADT code. This should really
be done inside the southbridge wrapper and not in the mainboard,
but for now the code to attach it to is inside the mainboard.
Update Kconfig for parmer and thatcher to default to legacy free.
Change-Id: Ib899bd02ddc5506caae4aca2c589cc2526638cb8
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2157
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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Change-Id: I2f10909a626fb64c7f95663ddd79a3b899f73bc4
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1606
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
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Change-Id: I0b10080deb971cdefa4d3916fabd40f5a81b11f4
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1352
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This is for GfxInitSview(GnbSview.c). It would create warning message if it
could not get VBIOS image.
Change-Id: I3b2726f612b4b7a237644a4b63b56efad52b7ab5
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1351
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Parmer has.
1. Trinity, Socket FS1R2.
2. Hudson A75.
Ubuntu has been validated on Parmer. S3 is supported.
Change-Id: I1a6932d0ca9f7abe78dc24d3bc238a4b5a48281b
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1158
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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