coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2023-11-10	device/Kconfig: rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORT	Felix Held
	Rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORT and add a help text to this Kconfig option to clarify what this option is about. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71e36869c6ebf77f43ca78f5e451aebfb59f1c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-02-28	mb/amd/gardenia,pademelon/mainboard: use ACPI_SCI_IRQ definition	Felix Held
	Use the ACPI_SCI_IRQ definition for both the PIC and APIC IRQ number in the fch_irq_map table. Before the PIC mapping was set to PIRQ_NC, but both mb/google/kahlee and the other amd mainboards using newer SoCs set both the PIC and APCI IRQ number to ACPI_SCI_IRQ, so change this here to match the other mainboards. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I29dde7ca8d2ecf00d8174c2d793ef1ad55ae3e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73322 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31	mb/amd: Include <gpio.h> instead of <soc/gpio.h>	Elyes Haouas
	<gpio.h> chain-include <soc/gpio.h>. Change-Id: I48191064fcee53ca843a537aa36bdbbd57736bf2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-07	mb/amd: Update pademelon to eval board	Martin Roth
	While pademelon may be a desktop board, it's not available for purchase, which means it should be presented here as an eval board. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5038935bb6f2ba530ea6e16ac84c1746efec8e48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-27	mainboard/acpi: Replace constant "Zero" with actual number	Felix Singer
	Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-15	soc/amd: commonize generation of the PIC/APIC mapping tables	Felix Held
	Now that we have a common init_tables in all mainboards using AMD SoCs, both the population of the fch_pic_routing and fch_apic_routing arrays and the definition of those arrays can be moved to the common AMD SoC code to not have the code duplicated in all mainboards. BUG=b:182782749 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15	mb/amd/gardenia,pademelon: rewrite IRQ mapping handling	Felix Held
	Gardenia and Pademelon had the same mainboard_picr_data and mainboard_intr_data data arrays. Compared to Kahlee there were 4 differences for PIRQ_F, PIRQ_SCI, PIRQ_SD and PIRQ_SATA in the IRQ data arrays. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia460b467990be7c3e6261440505988a9770ea084 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68852 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26	soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIES	Felix Held
	Instead of using magic constants for the fch_pic_routing and fch_apic_routing array sizes, define FCH_IRQ_ROUTING_ENTRIES in the common code headers and use this definition. This also allows to drop the static assert for the array sizes. In the Stoneyridge mainboard code the equivalent arrays are named mainboard_picr_data and mainboard_intr_data; also use FCH_IRQ_ROUTING_ENTRIES as fixed array size there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68818 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-15	mb/amd/padmelon: rename to pademelon	Felix Held
	This AMD reference board is called Pademelon and not Padmelon, so fix the name in coreboot. Also update the corresponding documentation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id1c7331f5f3c34dc7ec4bc5a1f5fe3d12d503474 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>