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2021-02-12soc/amd: Move fadt device tree settings into common_configRaul E Rangel
This is ACPI specific config that applies to all the AMD SoCs. Stoney doesn't currently use this, but we can add that functionality later. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16soc/amd/picasso: Fix the typo in GPIO defineZheng Bao
Change-Id: I8c9eed5d0e320b02382c24304a44e51e89eb6ac5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04mb/amd/mandolin: Unify devicetree formatting for 00:14 devicesPaul Menzel
To accommodate also `off`, two spaces are used after `on` to align comments. This unifies the devicetree files of the two variants. Change-Id: I7908fe2313ddccb6a4448a6338d6cd4938264f62 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04mb/amd/mandolin: mandolin: Fix typo in *Coprocessor* in commentPaul Menzel
This reduces the difference with Cereme’s devicetree file. Change-Id: I1e6ba5891245562d5132307eab224623031e11c8 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04mb/amd/mandolin: use more readable size formats in FMAP filesFelix Held
Since the FMD file isn't parsed any more by a shell script in the SoC's Makefile.inc, we can use better human-readable numbers for the section sizes. TEST=Timeless build results in identical image. Change-Id: I2117064a694f67767284f6fd4ac3604b254a2734 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-23mb/google/zork: correct USB2 phy TXVREFTUNE0 parameter nameKevin Chiu
From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0". correct rx_vref_tune -> tx_vref_tune BUG=None BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-30mb/amd: Add Pollock CRB Cereme as Mandolin variantFelix Held
Even though the devicetrees of Mandolin and Cereme are relatively similar, they are kept as separate files instead of using devicetree overrides to facilitate creating mainboard ports based on those CRBs. The two boards are reference boards for different zen/zen+ APU platforms that share the silicon, but use different packages. This is also consistent with the google/zork boards that have two different full base devicetrees for the two different platforms and then use devicetree overrides for the different variants of the two reference designs. BUG=b:159617786,b:169644059 BRANCH=zork Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42786 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30mb/amd/mandolin: add missing SPI configuration to devicetreeFelix Held
This fixes the board not booting reliably when running from flash without the EM100 option selected during build time. Selecting EM100 mode overrides the settings, so when testing with an EM100 I didn't run into this issue. BUG=b:169644059 BRANCH=zork Change-Id: I2c7043c174dcf4501776a03b7689d8a20c214afb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45830 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23mb/amd/mandolin: simplify flashmap fileFelix Held
Now that we're using fmaptool to parse the .fmd file, we can use some short forms and omit unnecessary information. BUG=b:157068645 TEST=Timeless build for amd/mandolin resulted in identical binary. BRANCH=zork Change-Id: I196c7857f165e75b543c1bda650e044b5ad0664e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-14soc/amd/picasso: Move sd_emmc_config into emmc_config structRaul E Rangel
I plan on adding another eMMC parameter. This refactor keeps the config contained in a single struct. BUG=b:159823235 TEST=Build test Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31mb/amd/mandolin: move PCIe GPP clock setting to devicetreeFelix Held
Checked with the schematics that all PCIe clocks have a corresponding clock enable pin. BUG=b:149970243 BRANCH=zork Change-Id: If96cdf95e213682217e46a98fc69c5c2ef4a148d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44892 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/amd/mandolin: fix AUX/HDP mapping for last DDI port on DaliFelix Held
We hit a similar issue on Cereme, so I checked the trembyle base board which also uses AUX4/HDP4 for the last DDI port, so using AUX3/HDP3 is wrong there. Change-Id: I99f9426969488cc5c5a14bd432b38bfd69ae7ef0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2020-08-18mb/amd/mandolin: enable SoC UARTs 0 and 1 and disable 2 and 3Felix Held
There are only headers for the SoC's UART 0 and 1 on the board. BUG=b:165020060 TEST=Linux only detects UART 0 and 1. Change-Id: I45929f65a5f844ae5cef792b11176f487c80766f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44530 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-15mb: remove unnecessary FADT flag devicetree entries for PicassoFelix Held
Those flags already get unconditionally set in soc/amd/picasso/acpi.c. Change-Id: I978c7d67480499d92c193d5bb87bc876211187db Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-28mb/amd/mandolin: remove ACPI_FADT_RESET_REGISTER from fadt_flagsFelix Held
This applies what commit 79572e4f32f844f60338d1aafdba6b94f4111a5c does to the devicetree settings of amd/mandolin. Change-Id: I6cc0a2b60b13a809016225caf3c89f730deb4ce0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-27mb/amd/mandolin: add USB over-current pin mapping to devicetreeFelix Held
The over-current pin mapping matches the board schematics. Change-Id: I23fd208680dcb52f5adaa144f00cb46bc7a21b91 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26mb/amd/mandolin: add default USB2 PHY tune parameters to devicetreeFelix Held
Change-Id: I4ea2fb83522d8810fe84e0a3f42bf44f2f911461 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43819 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23amd/picasso: rename PCIe descriptor to DXIO descriptorFelix Held
Most of the DXIO descriptors are used to configure PCIe engines and lanes, but on Picasso system some of the DXIO lanes can also be configured as SATA or XGBE ports. Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23vc/amd/fsp/picasso: add logical to lane number in port descriptor structFelix Held
The lane numbers in the PCIe/DXIO descriptor are the logical and not the physical ones, so add logical to the corresponding field names of the fsp_pcie_descriptor struct. Change-Id: I7037fed225119218e87593932815aff815e83ff8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16soc/amd/picasso: remove unused fadt_pm_profile devicetree settingFelix Held
commit 56da63c3dc3f50cfac541c779b608e1bae9e635c removed overriding that field in the FADT. Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/amd/mandolin: add SATA DXIO descriptor for Dali SKUsFelix Held
Dali supports two SATA ports, but no PCIe alternate function on those pins. Change-Id: I27a13100e80565eb1dade2d703ba3d1f8b5f630f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16mb/amd/mandolin: fix DXIO lane numbersFelix Held
The DXIO descriptors use the logical and not the physical lane numbers, which are different. Change-Id: I7a90056d782d8d32fe34a0f5bdb61c3b61df1af8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-06mb/amd/mandolin: Drop SPD eeproms in devicetreeKyösti Mälkki
Even with previous platforms, these entries were not utilised for raminit. Change-Id: I9a9a1a292bad8c4c89cbacb826c80f4098cae00f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-29mb/amd/mandolin: make mandolin a variant of itselfFelix Held
A follow-up patch will add Cereme which is a Mandolin variant. Beware that the name of the EC firmware image is changed from mchp.bin to EC_mandolin.bin. TEST=Mandolin still boots into Linux live system. Change-Id: Ifee91306756f8a4152a6a0224e172dae7eac8f7a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42785 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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