coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-02-12	soc/amd: Move fadt device tree settings into common_config	Raul E Rangel
	This is ACPI specific config that applies to all the AMD SoCs. Stoney doesn't currently use this, but we can add that functionality later. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16	soc/amd/picasso: Fix the typo in GPIO define	Zheng Bao
	Change-Id: I8c9eed5d0e320b02382c24304a44e51e89eb6ac5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04	mb/amd/mandolin: Unify devicetree formatting for 00:14 devices	Paul Menzel
	To accommodate also `off`, two spaces are used after `on` to align comments. This unifies the devicetree files of the two variants. Change-Id: I7908fe2313ddccb6a4448a6338d6cd4938264f62 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04	mb/amd/mandolin: use more readable size formats in FMAP files	Felix Held
	Since the FMD file isn't parsed any more by a shell script in the SoC's Makefile.inc, we can use better human-readable numbers for the section sizes. TEST=Timeless build results in identical image. Change-Id: I2117064a694f67767284f6fd4ac3604b254a2734 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-23	mb/google/zork: correct USB2 phy TXVREFTUNE0 parameter name	Kevin Chiu
	From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0". correct rx_vref_tune -> tx_vref_tune BUG=None BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-30	mb/amd: Add Pollock CRB Cereme as Mandolin variant	Felix Held
	Even though the devicetrees of Mandolin and Cereme are relatively similar, they are kept as separate files instead of using devicetree overrides to facilitate creating mainboard ports based on those CRBs. The two boards are reference boards for different zen/zen+ APU platforms that share the silicon, but use different packages. This is also consistent with the google/zork boards that have two different full base devicetrees for the two different platforms and then use devicetree overrides for the different variants of the two reference designs. BUG=b:159617786,b:169644059 BRANCH=zork Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42786 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>