coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-06-07	soc/amd/cezanne: Configure I2C Pad RX Select through devicetree	Karthikeyan Ramasubramanian
2021-05-27	mb/amd/majolica: enable crypto coprocessor PCIe device	Felix Held
2021-05-27	mb/amd/majolica: set PSPP policy to balanced	Felix Held
2021-05-14	mb/amd/majolica: Disable IO ports 0x60/0x64	Raul E Rangel
2021-05-06	soc/amd/common/espi,mb/: Allow configuring open drain ALERT#	Raul E Rangel
2021-05-06	mb/amd/majolica: Enable S0i3 by default	Jason Glenesk
2021-04-16	soc/amd/cezanne: Add uart controllers to chipset.cb	Ivy Jian
2021-04-07	mb/amd/majolica: add PCIe devices to devicetree	Felix Held
2021-03-25	mb/amd/majolica: Enable IO port 2E/2F	Zheng Bao
2021-03-11	mb/amd/majolica: Enable USB ACPI in devicetree	Mathew King
2021-03-03	mb/amd/majolica: Add eSPI support	Zheng Bao
2021-03-02	mb/amd/majolica: Enable required devices in devicetree	Mathew King
2021-02-14	soc/amd/cezanne: move CPU cluster to chipset device tree	Felix Held
2021-02-12	mb/amd/majolica/devicetree: add CPU cluster	Felix Held
2020-12-05	mb/amd/majolica: add skeleton of Cezanne reference board	Felix Held