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path: root/src/mainboard/amd/majolica/Kconfig
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2023-09-01util/amdfwtool: Deal with psp position in flash offset directlyZheng Bao
It is based on work by Arthur Heymans, 69852. Get rid of the confusing "position index" and use the relative flash offset as the Kconfig setting instead. TEST=binary identical on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst (The test should be done with INCLUDE_CONFIG_FILE=n) Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-22mb/amd/majolica: Add default setting PSP_INIT_ESPIZheng Bao
The board needs this setting to boot. Change-Id: I7f507c2478b63daf891430e95b008747b9b95a51 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-05-24mb/amd/chausie,majolica: don't select HAVE_ACPI_RESUMEFelix Held
The Chausie and Majolica boards use S0ix which is mutually exclusive with S3, so don't select HAVE_ACPI_RESUME. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d1bf33ad017dfbf908e0a195949998668c8e137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64605 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/(amd,google): Update SPI Kconfig settings based on devicetreeMartin Roth
This takes the devicetree SPI settings and moves them into Kconfig. BUG=b:195943311 TEST=boot guybrush & majolica and verify spi settings. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Icce1d57761465ae8255e5d9ce8679f3fdcb0ceed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-27mb/amd/majolica/Kconfig: add EFS SPI settingsFelix Held
This keeps the default of EFS_SPI_SPEED at 66.66Mhz for the non-EM100 case, but switches the EFS_SPI_READ_MODE setting from Dual IO (1-1-2) to Quad IO (1-1-4) for the non-EM100 case. This patch adds a special config for the EM100 emulator case that has limited SPI frequency support. Tested on Majolica by Martin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8996c2bf606ccd21686092beac8d96b22c0b7869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56815 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `FMDFILE` onceAngel Pons
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/amd/majolica,google/guybrush,google/mancomb: select HAVE_ACPI_RESUMERaul E Rangel
Since not all mainboards based on the Cezanne SoC have to support ACPI resume, select this option in the mainboard's Kconfig and not in the SoC's Kconfig. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I988276ccb5b61837d7f3f015d1d1aba783324b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03mb/amd/majolica: Add eSPI supportZheng Bao
Change-Id: I3e82a51173f561df560c36528a9b7ec26cf489b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-11mb/amd/majolica: Add chromeos supportRaul E Rangel
This change enables vboot support. To use it add CHROMEOS=y to your config. TEST=Boot majolica and see verstage run, and then see depthcharge load. coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 verstage starting (log level: 8)... Phase 1 FMAP: area GBB found @ 805000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 Phase 2 Phase 3 FMAP: area GBB found @ 805000 (458752 bytes) FMAP: area VBLOCK_A found @ 30000 (8192 bytes) FMAP: area VBLOCK_A found @ 30000 (8192 bytes) VB2:vb2_verify_keyblock() Checking keyblock signature... VB2:vb2_verify_digest() HW RSA forbidden, using SW VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW FMAP: area VBLOCK_A found @ 30000 (8192 bytes) FMAP: area VBLOCK_A found @ 30000 (8192 bytes) VB2:vb2_verify_fw_preamble() Verifying preamble. VB2:vb2_verify_digest() HW RSA forbidden, using SW VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW Phase 4 FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes) VB2:vb2api_init_hash() HW crypto forbidden by TPM flag, using SW VB2:vb2_verify_digest() HW RSA forbidden, using SW VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW Saving secdata firmware Saving secdata kernel Saving nvdata Slot A is selected FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes) CBFS: mcache @0x02017000 built for 9 files, used 0x1ec of 0x800 bytes CBFS: Found 'fallback/romstage' @0x0 size 0x753c in mcache @0x02017000 BS: verstage times (exec / console): total (unknown) / 116 ms coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 romstage starting (log level: 8)... Family_Model: 00a50f00 FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes) CBFS: Found 'fspm.bin' @0x15440 size 0x2257d in mcache @0x02017138 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I43f0c6e33649332057f41f8813a86571b06032f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-04mb/amd/majolica: add fmd for use when building chromeosMathew King
BUG=b:177909472 TEST=builds Change-Id: I5eb3c60fe60e4029485fae642c88c5c013ffb3f6 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50208 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22mb/amd/majolica: Add PSP support for board majolicaZheng Bao
Change-Id: Ia2470a7297c7003c7975c7d9b977f2f97174efea Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48529 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18mb/amd/majolica: Add option of ROM sizeZheng Bao
Change-Id: I07740285658aa098d3785cbead173b2f3acca42d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-14mb/amd/majolica: use integrated UART as consoleFelix Held
Change-Id: Ic6dcbe999234f233fbac8fbdb06d22c8577b1a40 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11soc/amd/cezanne: add 0xcf9 resetFelix Held
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05mb/amd/majolica: add functionality to add EC blob to buildFelix Held
Without the EC blob being present in the SPI flash, the board won't even power up. Change-Id: Ia3c50e86414bbc707bc33e28c636196c1be2f1e6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-05mb/amd/majolica: add skeleton of Cezanne reference boardFelix Held
This is an adapted copy of mainboard/example/min86 that is currently only used for Jenkins to test the SoC code in soc/amd/cezanne and isn't expected to reach boot block at the moment. It will be extended in future follow-up commits. Change-Id: I6806955952fbfa3227294cfc44fdf9156140e933 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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