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Made using coccinelle:
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expression E;
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-(E + 7) & -8
+ALIGN(E, 8)
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expression E;
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-(E + 15) & -16
+ALIGN(E, 16)
Change-Id: I071d2c98cd95580d7de21d256c31b6368a3dc70b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/910
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Fix the copy-paste typo in ALIB table creation. ssdt is useless here.
Change-Id: I250066eb5f755275f75c37789ce8760de35b046b
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/885
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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The name of processor created by AGESA is P00n, whose P is
BLDCFG_PROCESSOR_SCOPE_NAME(is 'C' if it is undefined.) and n starts
from 0. The dsdt should be aligned with that.
This feature has only been tested on persimmon. The changes on all the
other boards were propagated.
Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/884
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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Change-Id: I65d50616e49802b7bb13f02369c4898fa4a238a4
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/903
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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HEST feature starts from ACPI 4.0.
HEST is one of four kinds of tables of ACPI Platform Error
Interfaces (APEI). In Windows world, APEI is called Windows Hardware
Error Architecture (WHEA).
APEI consists of four separate tables:
1. Error Record Serialization Table (ERST)
2. BOOT Error Record Table (BERT)
3. Hardware Error Source Table (HEST)
4. Error Injection Table (EINJ)
All these 4 tables have the same header as FADT, MADT, etc. They are
pointed by RSDP.
For the HEST, it contains the error source. The types of them are
defined as
type description
1. Machine Check Exception (MCE)
2. Corrected Machine Check (CMC)
3. NMI Error
6. PCI Express Root Port AER
7. PCI Express Device AER
8. PCI Express Bridge AER
9. Generic Hardware Error Source
Error source types 3, 4, and 5 are reserved for legacy reasons and
must not be used.
Currently AMD board only provide part of "Machine Check
Exception (MCE)" & Corrected Machine Check (CMC)". we need to provide
the header of each error source. Other types of Error Sources is in
TODO list.
Only persimmon is tested. Linux can add HEST feature. The dmesg says,
ACPI: HEST 0000000066fe5010 00198 (v03 CORE COREBOOT 00000000 CORE 00000000)
......
HEST: Table parsing has been initialized.
No more message is got.
Windows can boot with this patch. Havent found a way to test it.
Change-Id: I447e7f57b8e8f0433a145a43d0710910afabf00f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/888
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
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Change-Id: I0cbb5f7fce91fe65fe8daad00fc43e68337783b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/832
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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We used several names for that same value, and hardcoded the value
at some more places.
They're all LOCAL_APIC_ADDR now (except for lapic specific code
that still uses LAPIC_DEFAULT_BASE).
Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/676
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Dinar mainboard is an AMD evaluation board for
Orochi Platform family15 model 00-0f processor.
The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets.
16 cores InterLagos Opteron processor are supported.
Windows 7 are verified on this platform.
Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/564
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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