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path: root/src/mainboard/amd/dinar/agesawrapper.c
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2014-12-20AGESA: Add amd_initcpuio() and amd_initmmio()Kyösti Mälkki
These are not wrappers for AGESA as they do not enter vendorcode at all. We expect most of the added fixme.c file to be written without use of AMDLIB.h and parts relocated as northbridge enable_resources(). Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7815 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03AGESA fam15: Common agesawrapperKyösti Mälkki
Place empty OemCustomizeInitEarly() and OemCustomInitPost() in a common file for now and split eventlog parser to a separate file. Change-Id: Ia8277ad13a800898b3e1a4e9c8fbd838ae2efeae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7155 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03AGESA: Report events with AGESA_EVENTLOG()Kyösti Mälkki
NOTE: For fam12 and fam14 ASSERT() is defined empty so execution may fall through critical failures. Change-Id: Ifef65d749d340f1df3a43b5fcb38c4315ef944e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7154 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA: Use common header for agesawrapperKyösti Mälkki
Change-Id: I5189d0c55635aeb29553fd04a67490cfee3d88d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7153 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-20vendorcode/amd/agesa/f*/Porting.h: Sync files across fam'sEdward O'Callaghan
Sync up these 'Porting.h' headers to include fixes from each family on botched-up typedef's for primitive data types. Fix corresponding breakage introduced by typecasts in mainboards. Change-Id: I003b155cc6c860f6b0cd75667083634a04814473 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7512 Tested-by: build bot (Jenkins)
2014-10-22amd/torpedo amd/dinar: Sanitize agesawrapper headerKyösti Mälkki
Change-Id: I3badb18839773e38834de967a51c29a306975d20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7152 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-19AGESA: Drop board and chipset -specific callout headersKyösti Mälkki
Change-Id: If973f28931e65a57cbb8d6739542a57c844f0d66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7115 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AGESA: Fix error status code return type to enum from UINT32Edward O'Callaghan
AGESA correctly uses the enum AGESA_STATUS type whereas boards use a mess of UINT32 typecasts. Also no need to shout VOID. We are not that careful on changing all cases of VOID->void or whitespace issues as these files will get merged with follow-ups. Change-Id: I16ccfcc73cda6b917c7ff5fd42ee2cd04e7dc0dd Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6182 Tested-by: build bot (Jenkins)
2014-06-14mainboard/amd: De-ASCIIartify reference boardsEdward O'Callaghan
For anyone who knows the difference between a header and a variable in C these depictions are rather useless. Thus, these lines wast essential screen real estate while working on coreboot. Change-Id: I7fe55d936c035ef83832716c45bfc57d73c0edc7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5979 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-26AGESA fam12 fam15: Unify agesawrapper_amdlaterunaptaskKyösti Mälkki
Pass parameter Func like fam14, fam15tn and fam16kb. Change-Id: I262bf88e431f7035e668ac8f3fb29ac0690b3e52 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5681 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA: Implement EmptyHeap()Kyösti Mälkki
Heap allocation begins with BIOS_HEAP_MANAGER, no need to clear the fields individually. Change-Id: Ia1af84bd09d1edf8f72223752557d44a96dec6e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5659 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15: Add GetHeapBase()Kyösti Mälkki
While fam15 boards do not select HAVE_ACPI_RESUME, backport this from fam14. Implementation of this function is common across different families. Change-Id: I222b418a0a79bbdf5f5cce6c876243ecb4912256 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5655 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-15Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki
This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be set with values that are not power of 2. The region programmed as WB cacheable will include all of ROM_SIZE. Side-effects to consider: Memory region below flash may be tagged WRPROT cacheable. As an example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB. Since this can overlap CAR, we add an explicit test and fail on compile should this happen. To work around this problem, one needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and define a smaller region for WB cache. With this change flash regions outside CBFS are also tagged WRPROT cacheable. This covers IFD and ME and sections ChromeOS may use. Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4625 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2013-06-28AMD Dinar: Eliminate warnings (initializers/prototypes/unused var)Bruce Griffith
Fix a bunch of compiler-generated warning messages. These fixes are mainly braces for grouping initializers. These changes are not intended to change any code functionality. There are two changes where function prototypes are added, and two cases where unused variables are eliminated. Change-Id: I93cef8899170b5575e7fb7c55181b381a7bcd9d8 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3545 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-04AGESA boards: Fix grammar in description of `OemCustomizeInitEarly`Paul Menzel
The following command was used to correct the grammatical mistake. $ git grep -l 'This is the stub function will call' | xargs sed -i s,This is the stub function will call,This stub function will call, '{}' sed: -e Ausdruck #1, Zeichen 6: Nicht beendeter `s'-Befehl As this file seems to have been copied around a lot, it originally seems to have come with the following commit for AMD Persimmon and AMD Inagua. commit 69da1b676cd3f126b27a6fd3c23c557ac1a03961 Author: Frank Vibrans <frank.vibrans@amd.com> Date: Mon Feb 14 19:04:45 2011 +0000 Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8. Change-Id: I2e6630a5172738b01e6def7062284f167e5508b1 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2268 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-16Fix high dword of MTRR mask set with CONFIG_CPU_ADDR_BITSMartin Roth
Bits were being shifted off the end of the mask accidentally. This results in all masks being 32 bits wide instead of 48. Change-Id: I5f4d1b6a323df1aa4568ff4491f82447b8a2f839 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2146 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-11AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITSZheng Bao
The high bits of mtrr mask are MBZ (Must be zero). Writing 1 to these bits will cause exception. So be carefull when spread this change. The supermicro/h8scm needs more work. Currently it is set as it was. We need to check if the F10 and F15 have different value. Change-Id: I2dd8bf07ecee2fe4d1721cec6b21623556e68947 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1661 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-07-25AMD Family15tn: Set the mask of MTRR to 0000FFFXX0000800zbao
Remove the warning message from linux dmesg, mtrr: your BIOS has configured as incorrect mask, fixing it. Change-Id: I355509db12ab10c33b7c1c23e2c7c4783f30e67e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1349 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-02-17Mainboard: Add AMD dinar mainboard.Kerry Sheh
Dinar mainboard is an AMD evaluation board for Orochi Platform family15 model 00-0f processor. The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets. 16 cores InterLagos Opteron processor are supported. Windows 7 are verified on this platform. Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/564 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
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