coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2022-02-03	mb/amd/chausie/devicetree: update I2C RX levels to match board design	Felix Held
	Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie5d5f5441132e5b0d8991d07d4dde994fc17ab64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03	soc/amd/*/i2c: factor out common I2C pad configuration	Felix Held
	The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-27	soc/amd/sabrina/chipset.cb: update USB ports	Felix Held
	The corresponding mainboard design guide was used as a reference here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie61af7dab35b560d2eec1ea62058f3a4dad5cb0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27	soc/amd/sabrina: update PCI devices in devicetree.cb	Felix Held
	Also update mb/amd/chausie accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb4dcffa48c3dbdcffb66f1398b99ee96562efb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25	mb/amd/chausie: add mainboard as copy of mb/amd/majolica	Felix Held
	To have the new AMD Sabrina SoC code tested, add the AMD Chausie mainboard as a copy of Majolica. This patch also changes the name from Majolica to Chausie, selects the Sabrina SoC instead of the Cezanne SoC and comments out the APCB_SOURCES since those aren't available in the 3rdparty/blobs repository yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic7b18f7a6ae5b8365234dd1227e0b1f7f37279da Reviewed-on: https://review.coreboot.org/c/coreboot/+/61079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>