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The APOB data in DRAM is larger than the 96 kBytes of RW_MRC_CACHE, so
it won't fit in the flash and makes soc_update_apob_cache return early
before writing the APOB data from DRAM into the flash with this warning:
[WARN ] RAM APOB data is too large 1db18 > 18000
Increasing the RW_MRC_CACHE size to 120 kByte fixes this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I763d20f504d4f5b7cea68f21f409de9a1035f440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64555
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To have enough space in the A/B RW sections, increase those sizes to 4
MByte and decrease the RO section size to 6 MByte to free up the space
needed for that.
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Only the info about the location of the EC firmware will be stored right
at the beginning of the flash, so the size can be reduced to 4kByte
which is the erase block size of the flash. The CHAUSIE_MCHP_SIG_FILE
file itself is smaller than this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icde5f7071183cd8423fc022caf49e2c9ee288527
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62189
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On Sabrina SoCs the size of the APOB has increased, so the size of the
RW_MRC_CACHE FMAP sections needs to be increased in order for the data
to still fit in the corresponding FMAP partition.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib31b918aba90dd507b47aec9e1f75c138857cd02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62155
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To have the new AMD Sabrina SoC code tested, add the AMD Chausie
mainboard as a copy of Majolica. This patch also changes the name from
Majolica to Chausie, selects the Sabrina SoC instead of the Cezanne SoC
and comments out the APCB_SOURCES since those aren't available in the
3rdparty/blobs repository yet.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic7b18f7a6ae5b8365234dd1227e0b1f7f37279da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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