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2021-06-17soc/amd/picasso: introduce and use devicetree aliases for UART0-3Felix Held
Since the default state of the MMIO UART devices in the chipset devicetree is off, the mainboard devicetree entries that disable MMIO UART devices are removed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I913a587802020ce4e182b48632cdde1104c2a6e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55545 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01mainboards using soc/amd/picasso: use aliases for remaining PCIe devicesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id2bdce5871f57e9edb17f89cba61b5c5ae018566 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01soc/amd/picasso: introduce and use chipset device treeFelix Held
The chipset devicetree only has the essential PCIe devices enabled that are needed for the SoC code to work. It also defines aliases for all PCIe devices that can be used to reference the devices in the mainboard- specific devicetrees and devicetree overrides. To make the change easier to review that part will be done in a follow-up patch. Despite missing in the PPR, device pci 18.7 exists on Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-28mb/amd/bilby,cereme,mandolin: change PSPP policy to balancedFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7571ed92b3c3fa79581e2c7342960ca31451af1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-27soc/amd/picasso: add devicetree setting for PSPP policyFelix Held
Since the default for the corresponding UPD of the Picasso FSP is DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE, add a deviectree setting for each board that's using the Picasso SoC code to not change the setting for the existing boards. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-06soc/amd/common/espi,mb/: Allow configuring open drain ALERT#Raul E Rangel
Some designs might wish to use an open drain eSPI ALERT#. This change adds an enum that allows setting the eSPI alert mode. BUG=b:187122344, b:186135022 TEST=Boot guybrush using all 3 alert modes Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-29soc/amd/common/acp: Move Audio Co-processor driver to commonKarthikeyan Ramasubramanian
Audio Co-processor driver is similar for both Picasso and Cezanne SoCs. Hence move it to the common location. BUG=None. TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards. Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-20mainboard: Drop redundant DEVICETREE configurationFelix Singer
`devicetree.cb` is the default value for the Kconfig DEVICETREE setting. Drop redundant configurations. Change-Id: I5eded3d5e38ca80986da2fda95050815c2702f82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52504 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-12mb/amd/bilby: Use Picasso VBIOS as defaultRitul Guru
use PicassoGenericVbios.bin as default instead of raven VBIOS for Bilby. Change-Id: I99621173a33a1154f8bb4929d199288265bbe04d Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52209 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/amd/bilby: Enable postcode on port 0x80Ritul Guru
selecting SOC_AMD_COMMON_BLOCK_USE_ESPI will disable the lpc decodes, so not selecting that keeps the lpc decodes. Change-Id: I03a8d4b804cee205b9e06b00e2e5a442452f8f86 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52016 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/amd/bilby: enable boot from NVMe SSDRitul Guru
These changes involve NVMe specific GPIO programming to enable pcie NVMe SSD boot. Add nvme dev,func in devicetree and also remove unused GPIOs programmed in Bilby. Change-Id: I4407f82122c04b13684d4176ba5cd5a9fe03f0db Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51674 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08soc/amd,mb/google/,mb/amd: Move sleepstates.aslRaul E Rangel
This file is common for all the AMD platforms. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I10ee600b4bcd7aaff39bfab075eb4dbc9096b435 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51299 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01mb/: Drop print of MAINBOARD_PART_NUMBERKyösti Mälkki
Change-Id: Ie3870bc666acaea316f00b205de512cf790e720c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-24mb/amd,google: Rename static functions to mainboard_enableKyösti Mälkki
Let's not have 7 boards of all use a different name for the .enable_dev function in mainboard chip_operations. Change-Id: I07f3569e6af85f4f1635595125fe2881ab9ddd43 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-24mb/amd,google/zork: Move init_tables() callKyösti Mälkki
The semantics of pirq_setup() from previous platforms was to only setup the global pointers for PIC and APIC tables, not to create or modify the tables themselves. Change-Id: Iaa7c31eed21432dc2b3fe6b32803bd2658fd5e2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-22mb/amd/bilby: updating EC FW specific options for bilbyRitul Guru
EC does not exist in Bilby platform, so removing EC size from board.fmd and updating bilby fmap size to 0xfef000. Removing unused EC FW config options MANDOLIN_HAVE_MCHP_FW and MANDOLIN_MCHP_FW_FILE. Change-Id: I9ca4e421b0d80d041ed4046fa20cc16e24a776d0 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-17mainboard/amd/bilby: Add Bilby CRB boardRitul Guru
Bilby is the reference board for AMD Raven, Raven2 and Picasso APUs. Bilby mainboard code is taken from mandolin variant Cereme. These new files are a renamed copy and subsequent patches will be applied to create a working bilby implementation. Change-Id: I426966d782e259a971ec36bac2498bc62b4ce7e2 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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