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2019-11-20mb/*/*: Drop AMDFAM10 mainboardsArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-28mb/*/*/Kconfig: Remove useless commentElyes HAOUAS
Change-Id: Ibdff50761a205d936b0ebe067f418be0a2051798 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hellsenberg <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-16src/mainboard: Remove unused "HW_MEM_HOLE_SIZE_AUTO_INC"Elyes HAOUAS
Change-Id: I10e89de270a20dbd28647e8b0f8a2425c515b350 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-01-04amdfam10: Perform major include ".c" cleanupDamien Zammit
Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/17625 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2015-08-23AMD Kconfig: Remove QRANK_DIMM_SUPPORT from unsupported platformsMartin Roth
The AMD K8 northbridge uses the Kconfig symbol QRANK_DIMM_SUPPORT, but the symbol was used on a number of Family 10 boards as well. AMD Family 10 doesn't use this Kconfig symbol for anything. I verified that the symbol wasn't used actually getting used in any of these platforms. Fixes Kconfig warnings for these 19 mainboards: warning: (BOARD_SPECIFIC_OPTIONS...) selects QRANK_DIMM_SUPPORT which has unmet direct dependencies (NORTHBRIDGE_AMD_AMDK8) Change-Id: I454992a4975566fd6439a21f5a800d0cfa1b4d3b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11300 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-06-05AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0Kyösti Mälkki
If SB_HT_CHAIN_ON_BUS0 is selected, HyperTransport chain for System Bus is the first to scan and it will be assigned with bus number 0. If HT_CHAIN_DISTRIBUTE is selected, each link will reserve a fixed range of bus numbers instead of assigning consecutive numbers across all the links. All fam10 have SB_HT_CHAIN_ON_BUS0 selected under northbridge. Follow-up can easily drop this if we find this is dictated by architecture. Change-Id: I8deddcb4c3fd679b6b27e2879d9dba3895c4dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8366 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-04-28Kconfig whitespace fixesMartin Roth
trivial whitespace fixes. Mostly changing leading spaces to tabs. Change-Id: I0bdfe2059b90725e64adfc0bdde785b4e406969d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09AMD fam10: Always have AMDMCTKyösti Mälkki
Also drop some more #if UNUSED_CODE. Change-Id: I1bbe96a65c9240636ff7cfaf70c2ecbfb3aee715 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8551 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-02-03amd/model_10xxx: Drop AMD_UCODE_PATCH_FILE selectionKyösti Mälkki
Include microcode updates in CBFS for every CPU revision the platform can support, as changing to different CPU revision should not require a coreboot rebuild. This increases CBFS usage from 2 kB to 14 kB. Change-Id: I6bf90221a688f1a54e49641ce3ba378c5bf659f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4521 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2014-11-14AMD: Move RAMBASE and RAMTOPKyösti Mälkki
There are no reasons to not load ramstage @ 0x100000. Boards with HAVE_ACPI_RESUME enabled have performance penalty in using excessive RAMTOP. For these boards, this change releases 11 MiB of RAM from CBMEM allocation to OS. Change-Id: Ib71995aba5e9332d0ec1626b3eb3b4ef6a506d1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7094 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-05-10Replace SERIAL_CPU_INIT with PARALLEL_CPU_INITKyösti Mälkki
Lines with 'select SERIAL_CPU_INIT' where redundant with the default being yes. Since there is no 'unselect SERIAL_CPU_INIT' possibility, invert the default and rename option. This squelches Kconfig warnings about unmet dependencies. Change-Id: Iae546c56006278489ebae10f2daa627af48abe94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5700 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
CONFIG_ARCH is a property of the cpu or soc rather than a property of the board. Hence, move ARCH_* from every single board to respective cpu or soc Kconfigs. Also update abuild to ignore ARCH_ from mainboards. Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5570 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-12-29AMD fam10: Drop RAMINIT_SYSINFOKyösti Mälkki
AMD fam10 raminit cannot be built without RAMINIT_SYSINFO, this is not a true option but copy-paste remainder from AMD K8. Change-Id: Id8edc112f3bacebd1732304ac9ee6e77cc6263b7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-26AMD fam10: Drop MEM_TRAIN_SEQKyösti Mälkki
This config was for AMD K8 only. Change-Id: I76276405b676d1dd4d5dbf8c5b94194a670ccb25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4555 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-17AMD southbridges: Move HAVE_HARD_RESETKyösti Mälkki
All 3 boards with AGESA_HUDSON had HAVE_HARD_RESET with the reset.c file already placed under southbridge/. All 15 boards with CIMX_SBx00 had HAVE_HARD_RESET with functionally identical reset.c file under mainboard/. Move those files under respective southbridge/. Change-Id: Icfda51527ee62e578067a7fc9dcf60bc9860b269 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3486 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2012-11-16Fix Kconfig GENERATE_*_TABLE usageStefan Reinauer
Some boards selected GENERATE_ instead of HAVE_ Change-Id: I450c22d7b044f0c88c21692246d452d516a68a83 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1841 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16Drop unneeded BOARD_HAS_FADT optionStefan Reinauer
Change-Id: Iaaeee87d70cf052bc7980007cdf1f7dda88b3623 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-16Drop CONFIG_HAVE_BUS_CONFIG, clean up KconfigStefan Reinauer
This patch is the beginning of a Kconfig cleanup series - drop CONFIG_HAVE_BUS_CONFIG and add get_bus_conf.c if it exists in the mainboard directory - drop duplicate ACPI_SSDTX_NUM from mainboard Kconfig if it only defines the defaul value of 0 - Add mptable.c, fadt.c, reset.c and ssdtX.asl when they exist, not based on some Kconfig magic Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ia14a7116dad6a724af7e531920fee9a51fd0b200 Reviewed-on: http://review.coreboot.org/1832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-08-08Drop HAVE_MAINBOARD_RESOURCESKyösti Mälkki
These existed to provide a hook to add reserved memory regions in the coreboot memory table. Reserved memory are now added as resources. Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-31Revert "remove CONFIG_SERIAL_CPU_INIT"Sven Schnelle
This reverts commit 78efc4c36c68b51b3e73acdb721a12ec23ed0369. The broadcast patch was reverted, so this commit should also be reverted. The reason for reverting the broadcast patch: It turned out that sending IPIs via broadcast doesn't work on Sandybridge. We tried to come up with a solution, but didn't found any so far. So revert the code for now until we have a working solution. Change-Id: I05c27dec55fa681f455215be56dcbc5f22808193 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1380 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-02remove CONFIG_SERIAL_CPU_INITSven Schnelle
The new broadcast code doesn't support serial init - if a CPU needs serial init, this should be handled in the model specific CPU init code. Change-Id: I7cafb0af10d712366819ad0849f9b93558e9d46a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1140 Tested-by: build bot (Jenkins)
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n. This might break a couple of boards on runtime, but so far, fixes were quite simple. There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be adapted. Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07AMD SB800 southbridge updateKerry She
This patch enables access to the registers of the hardware monitor logical device in the superio via isa ports 0x295/0x296. Previously this was not enabled in the SB8xx LPC device. This is required for initialisation in init_hwm() in src/superio/winbond/w83627hf/superio.c and also by OS-level sensor monitoring such as lm-sensors to access temperature, fan monitoring and control and voltage registers. asrock/e350m1 and advansus/a785e-i mainboard changes are included herein. Change-Id: I2176885549277b335c0c41b48457d09b9b76b703 Signed-off-by: Per Hansen <perh52@runbox.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/159 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07AMD F14 southbridge updateKerry She
This change adds the southbridge related code to support the update of the AMD Family14 cpus to the rec C0 level. Some of the changes reside in mainboard folders but they reference changed files in the southbridge folder so they are included herein. Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-22Rename {CPU|NB|SB}/amd/*_wrapper foldersefdesign98
This change renames the cpu/amd/agesa_wrapper, northbridge/ amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and simplify the folder names. There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to append "ull" to a trio of 64-bit hexadecimal constants to allow abuild to run successfully. Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/51 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-04WARNINGS_ARE_ERRORS is y per default, don't set it twice.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-03advansus/a785e-i mainboard enable warning as errorKerry She
Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Kerry She <kerry.she@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-07ADVANSUS A785E-I Mainboard support, Family10h ASB2, RS880(RS785E) + SB820 ↵Kerry She
platform. Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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