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Objects that are created with acpigen need to be declared
with External () for the generation of dsdt.asl to pass
iasl without errors.
There are some objects that are common to all platforms,
and some that should be declared only conditionally.
Having a top-level ASL helps to achieve this.
Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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APIC was not referenced anywhere in ASL.
MPEN has references under boards:
getac/p470, roda/rk9, roda/rk886ex.
MPEN has reference also in Intel SpeedStep ASL.
Replace static MPEN with detection of multiple CPUs
installed.
Change-Id: Ib5f06416b23196b7227ccd5814162925c31c084b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Having some symmetry with <soc/nvs.h> now allows to reduce
the amount of gluelogic to determine the size and cbmc field
of struct global_nvs.
Since GNVS creation is now controlled by ACPI_SOC_NVS,
drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne
cannot have this selected until <soc/nvs.h> exists.
Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
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Rename acpi_create_gnvs() functions under mb/ to reflect
their changed functionality.
Remove now empty mb/acpi_tables.c files.
Change-Id: Ia366867ef73d1ade9805dc29b8e14b3073f44f60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48707
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Time has shown that using spaces never converges into proper alignment.
Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Most of these comments have been copy-pasted or serve no purpose other
than to eventually turn into misleading info. While the description of
the first 120 bits of CMOS could be useful, it should instead be added
to the documentation for the CMOS option infrastructure, or /dev/null.
Moreover, trim down newlines to no more than two consecutive newlines.
Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Adds a new port for the Aspire G43T-AM3. It is from an Aspire M3800
desktop model of which I only own the mainboard. The silkscreen label
calls it "G45T/G43T-AM3 V:1.0". In DMI data it is additionally called
Acer EG43M.
The Aspire M5800 model seems to use the same mainboard. The BIOS you can
download from Acer is identical for both.
Various similar mainboards by Acer exist: G41T-AM, G43T-AM, G43T-AM4,
Q45T-AM, to name a few. ECS has some models that are obiously based on
the same design, e.g. G43T-WM and G43T-M.
This model is a microATX-sized board with an LGA 775 socket, four DDR3
DIMM slots, one PCIe x16 slot, one PCIe x1 slot and two PCI slots based
on the Intel G43 chipset.
The port was started by copying mb/intel/dg43gt (not going to lie here)
and adapting things by looking at dumps from the system when running
with the vendor BIOS. Serial console output is possible by soldering to
a point at the corresponding Super I/O pin.
The service manual for the board was helpful for setting the correct PCI
IRQ links. It can be found publicly on the internet as the "Acer Aspire
M3800 Service Manual".
Working:
- CPUs from Pentium Dual-Core E2160 to Core 2 Quad Q9550 at FSB1333
- Native raminit
- All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB)
- PS/2 mouse
- PS/2 keyboard (needs CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500)
- USB ports (8 internal, 4 external)
- All six SATA ports
- Intel GbE
- Both PCI ports with various cards (Ethernet, audio, USB, VGA)
- Integrated graphics (libgfxinit)
- HDMI and VGA ports
- boot with PCIe graphics and SeaBIOS
- boot with PCI VGA and SeaBIOS
- Both PCIe ports
- Flashing with flashrom
- Rear audio output
- SeaBIOS 1.14.0 to boot slackware64
- SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS)
- Temperature readings (including PECI)
- Super I/O EC automatic fan control
- S3 suspend/resume
- Poweroff
Not working:
- Resource issues with the VGA BIOS of a PCI rv100-based card
- Super I/O voltage reading conversions
Untested:
- The other audio jacks or the front panel header
- On-board Firewire
- EHCI debug
- VBT (was extracted and added, but don't know how to test)
- Super I/O GPIOs
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I846cf5f4f1ef27fc644676a4c6f7a333e061f6cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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