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2022-12-05nb/intel/x4x: Remove apic 0 from devicetreeArthur Heymans
This is added at runtime. Change-Id: I7716f8a972e2280179aa6aee00488b22413c0c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69298 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-05cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfmArthur Heymans
C5, C6 and slfm depend on the southbridge and the northbridge to be able to provide this functionality, with some just lacking the possibility to do so. Move the devicetree configuration to the southbridge. This removes the need for a magic lapic in the devicetree. Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-01nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans
Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69295 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11src/mainboard: Remove unneeded whitespace before tabElyes HAOUAS
Change-Id: I37f12f5cb35ea1a6ad33edb114688ce1619030a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/acer/g43t-am3: add Acer G43T-AM3 mainboardMichael Büchler
Adds a new port for the Aspire G43T-AM3. It is from an Aspire M3800 desktop model of which I only own the mainboard. The silkscreen label calls it "G45T/G43T-AM3 V:1.0". In DMI data it is additionally called Acer EG43M. The Aspire M5800 model seems to use the same mainboard. The BIOS you can download from Acer is identical for both. Various similar mainboards by Acer exist: G41T-AM, G43T-AM, G43T-AM4, Q45T-AM, to name a few. ECS has some models that are obiously based on the same design, e.g. G43T-WM and G43T-M. This model is a microATX-sized board with an LGA 775 socket, four DDR3 DIMM slots, one PCIe x16 slot, one PCIe x1 slot and two PCI slots based on the Intel G43 chipset. The port was started by copying mb/intel/dg43gt (not going to lie here) and adapting things by looking at dumps from the system when running with the vendor BIOS. Serial console output is possible by soldering to a point at the corresponding Super I/O pin. The service manual for the board was helpful for setting the correct PCI IRQ links. It can be found publicly on the internet as the "Acer Aspire M3800 Service Manual". Working: - CPUs from Pentium Dual-Core E2160 to Core 2 Quad Q9550 at FSB1333 - Native raminit - All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB) - PS/2 mouse - PS/2 keyboard (needs CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500) - USB ports (8 internal, 4 external) - All six SATA ports - Intel GbE - Both PCI ports with various cards (Ethernet, audio, USB, VGA) - Integrated graphics (libgfxinit) - HDMI and VGA ports - boot with PCIe graphics and SeaBIOS - boot with PCI VGA and SeaBIOS - Both PCIe ports - Flashing with flashrom - Rear audio output - SeaBIOS 1.14.0 to boot slackware64 - SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS) - Temperature readings (including PECI) - Super I/O EC automatic fan control - S3 suspend/resume - Poweroff Not working: - Resource issues with the VGA BIOS of a PCI rv100-based card - Super I/O voltage reading conversions Untested: - The other audio jacks or the front panel header - On-board Firewire - EHCI debug - VBT (was extracted and added, but don't know how to test) - Super I/O GPIOs Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: I846cf5f4f1ef27fc644676a4c6f7a333e061f6cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/44167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>