coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-12-17	soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration	Benjamin Doron
2020-12-14	soc/intel/skylake: Drop always-zero ProbelessTrace dt setting	Angel Pons
2020-12-14	soc/intel/skylake: Drop unreferenced PttSwitch dt setting	Angel Pons
2020-11-13	soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig	Michael Niewöhner
2020-10-26	mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`	Michael Niewöhner
2020-08-08	soc/intel/skylake: Enable CIO depending on devicetree configuration	Felix Singer
2020-08-08	soc/intel/skylake: Enable SDXC depending on devicetree configuration	Felix Singer
2020-08-07	soc/intel/skylake: Enable thermal subsystem depending on devicetree	Felix Singer
2020-07-29	soc/intel/skylake: Enable HDA depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable eMMC depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable TraceHub depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable SMBus depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable LAN depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable SATA depending on devicetree configuration	Felix Singer
2020-07-26	skylake boards: Factor out copy-pasted PIRQ routes	Angel Pons
2020-05-18	skylake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-04	soc/intel/skl: always enable SataPwrOptEnable	Michael Niewöhner
2020-04-10	src/mb: Remove unneeded spaces before/after tabs	Elyes HAOUAS
2020-03-31	mb/51nb/x210: restore left USB3 port in devicetree	Matt DeVillier
2020-03-29	mb/51nb/x210: Fix up USB ports in devicetree	Matt DeVillier
2020-03-16	mb/51nb/x210: update devicetree	Matt DeVillier
2020-03-16	mb/51nb/x210: add libgfxinit support	Matt DeVillier
2020-03-16	mb/51nb: Add support for the 51nb X210	Matthew Garrett