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2022-03-09coreboot_tables.c: Expose the ACPI RSDPArthur Heymans
The ACPI RSDP can only be found in: - legacy BIOS region - via UEFI service On some systems like ARM that legacy BIOS region is not an option, so to avoid needing UEFI it makes sense to expose the RSDP via a coreboot table entry. This also adds the respective unit test. Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62573 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-09commonlib/bsd: Remove cb_err_tJulius Werner
cb_err_t was meant to be used in place of `enum cb_err` in all situations, but the choice to use a typedef here seems to be controversial. We should not be arbitrarily using two different identifiers for the same thing across the codebase, so since there are no use cases for serializing enum cb_err at the moment (which would be the primary reason to typedef a fixed-width integer instead), remove cb_err_t again for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-08timestamps: Rename timestamps to make names more consistentJakub Czapiga
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28lib/Makefile: Add ability to specify -ldflags for rmodulesRaul E Rangel
This will allow linker flag customization for rmodules. BUG=b:221231786 TEST=Build guybrush with patch train and verify ldflags are passed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib65476759e79c49d90856dcd7ee76d7d6e8a679a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-16Use the fallthrough statement in switch loopsArthur Heymans
Clang does not seem to work with 'fall through' in comments. Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-11lib/device_tree.c: Change 'printk(BIOS_DEBUG, "ERROR:' to printk(BIOS_ERR, "'Elyes HAOUAS
Change-Id: Ie20a2c35afc2b849396ddb023b99aab33836b8de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-07treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-07console: Add loglevel marker codes to stored consolesJulius Werner
In order to provide the same loglevel prefixes and highlighting that were recently introduced for "interactive" consoles (e.g. UART) to "stored" consoles (e.g. CBMEM) but minimize the amont of extra storage space wasted on this info, this patch will write a 1-byte control character marker indicating the loglevel to the start of every line logged in those consoles. The `cbmem` utility will then interpret those markers and translate them back into loglevel prefixes and escape sequences as needed. Since coreboot and userspace log readers aren't always in sync, occasionally an older reader may come across these markers and not know how to interpret them... but that should usually be fine, as the range chosen contains non-printable ASCII characters that normally have no effect on the terminal. At worst the outdated reader would display one garbled character at the start of every line which isn't that bad. (Older versions of the `cbmem` utility will translate non-printable characters into `?` question marks.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I86073f48aaf1e0a58e97676fb80e2475ec418ffc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-28lib/spd_cache.c: Drop comparison to {true, false}Elyes HAOUAS
Change-Id: I0ef8c0159c99606aad537fd5e14d3c74e32651d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-25lib/cbmem_console,console: Resurrect CONSOLE_CBMEM_DUMP_TO_UARTRaul E Rangel
Chromebooks normally run with non-serial enabled firmware because writing to the UART console is very slow. This unfortunately makes debugging boot errors more difficult. We tend to rely on port 80s and/or the vboot recovery code. When CONSOLE_CBMEM_DUMP_TO_UART is selected it will dump the entire cbmem console to the UART whenever `vboot_reboot()` is called. We don't incur any boot time penalty in the happy path, but still retain the ability to access the logs when an error occurs. The previous implementation was using a hard coded UART index and `get_uart_baudrate` was always returning 0 since `CONFIG_TTYS0_BAUD` wasn't defined. This change makes it so the UART console properties are available when CONSOLE_CBMEM_DUMP_TO_UART is set. This results in the following .config diff: +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_TTYS0_LCS=3 +CONFIG_CONSOLE_SERIAL_115200=y +CONFIG_TTYS0_BAUD=115200 This functionality is especially helpful on Guybrush. PSP Verstage is run on S0i3 resume. Today, if there is an error, the cbmem console is lost since it lives in the PSP SRAM. BUG=b:213828947, b:215599230 TEST=Build non-serial guybrush FW and verify no serial output happens in happy path. Inject a vboot error and perform an S0i3 suspend/resume. Verify CBMEM console gets dumped to the correct UART. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I997942204603362e51876a9ae25e493fe527437b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-23Makefile.inc: Add `-fno-pie` to `ADAFLAGS_common`Paul Menzel
Building libgfxinit with Debian’s toolchain – latest test with *gnat-11* 11.2.0-13 from Debian sid/unstable – the build fails with the error below. E: Invalid reloc type: 10 E: Unable to create rmodule from 'build/cbfs/fallback/ramstage.debug'. Debian’s toolchain is built without enabling PIE by default. So, explicitly pass `-fno-pie` to `ADAFLAGS_common` to be independent from how the toolchain was built. TEST=*gnat* 11.2.0-13 successfully. builds purism/librem_cnl/variants/librem_mini with libgfxint. With the coreboot toolchain `make BUILD_TIMELESS=1` produces the same `build/coreboot.rom` for `BOARD_PURISM_LIBREM_MINI_V2=y` on top of commit 50251400d2 (sb/intel/common/firmware: Reword me_cleaner warning) with and without the change. Change-Id: I6661937906d95c130c6099f598d61b21e958fd85 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-23lib/cbmem_console: Add cbmemc_copy_in functionRaul E Rangel
When running in verstage before bootblock, the PSP (ARM co-processor) is running with limited SRAM. It needs to stash the verstage console data internally until DRAM is brought up. Once DRAM is brought up the data is stashed in a "transfer buffer" region. In the current design, we are using the same region for the transfer buffer and the preram_cbmem_console region. This has the following downsides: 1) The pre-x86 buffer needs to be large enough to hold all the verstage, bootblock and romstage console logs. 2) On AMD platforms, the PSP verstage is signed. Changing the size of preram_cbmem_console after the fact will result in a mismatch of the transfer buffer between verstage and bootblock. This CL adds a new method that allows SoC specific code to copy the CBMEM console in the transfer buffer to the active CBMEM console. BUG=b:213828947 TEST=Boot guybrush and no longer see *** Pre-CBMEM romstage console overflowed, log truncated! Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idc0ab8090db740e0d1b3d21d8968f26471f2e930 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-21timestamp: Allow timestamp_add to accept a negative numberBora Guvendik
Change timestamp_add to accept negative values for events that took place before coreboot started executing. TEST=Boot to OS, check cbmem -t Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I90afc13a8e92693d86e3358f05e0a0cb7cdbca9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-21Revert "lib/cbmem_console: Move copy_console_buffer up in the file"Raul Rangel
This reverts commit 6a3bdf9aa5da6b620952c915330ce70702735456. Reason for revert: Oops, I thought I abandoned this. It's been replaced by https://review.coreboot.org/c/coreboot/+/61099/3 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id18e8e69481bdd78fdd70116940ea435922a9e77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-21lib/cbmem_console: Move copy_console_buffer up in the fileRaul E Rangel
This will make the method available earlier. This is needed for the next CL. BUG=b:213828947 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iee911a2debcfbf4309d2e866401b74f2a6c18feb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-17console/cbmem: Add cbmem_dump_consoleRaul E Rangel
This function is similar to cbmem_dump_console_to_uart except it uses the normally configured consoles. A console_paused flag was added to prevent the cbmem console from writing to itself. BUG=b:213828947 TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3fe0f666e2e15c88b4568377923ad447c3ecf27e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-17src: Remove unused <cbfs.h>Elyes HAOUAS
Found using: diff <(git grep -l '<cbfs.h>' -- src/) <(git grep -l 'cbfs_allocator_t\|cbfs_load\|cbfs_ro_load\|cbfs_type_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_preload\|cbfs_unmap\|cbfs_prog_stage_load\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_type\|cbfs_file_exists\|cbfs_ro_file_exists\|mem_pool\|cbfs_cache\|cbfs_boot_device\|cbfs_boot_device_find_mcache\|cbfs_boot_device\|cbfs_get_boot_device\|cbfs_init_boot_device\|cbfs_boot_lookup\|cbfs_alloc\|cbfs_unverified_area_alloc\|cbfs_default_allocator_arg\|cbfs_default_allocator\|cbfs_cbmem_allocator\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_load\|cbfs_type_load\|cbfs_ro_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_file_exists\|cbfs_ro_file_exists\|cbfs_mdata\|cbfs_find_attr\|cbfs_file_hash' -- src/)|grep "<" Change-Id: Ib4dca6da1eb66bbba5b6e94fd623f4fcfc2f0741 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14src/{drivers,lib}: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Ifad13ef418db204cf132fe00f75c6e66cd2bc51b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-13console/cbmem_console: Rename cbmem_dump_consoleRaul E Rangel
This function actually dumps cbmem to the UART. This change renames the function to make that clear. BUG=b:213828947 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icc314c530125e5303a06b92aab48c1e1122fd18c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-12src: Remove redundant <rules.h> and <commonlib/bsd/compiler.h>Elyes HAOUAS
<rules.h> and <commonlib/bsd/compiler.h> are always automatically included in all compilation units by the build system Change-Id: I9528c47f4b7cd22c5a56d6a59b3bfe53197cc4d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/lib: Remove unused <timer.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <timer.h>' -- src/) <(git grep -l 'NSECS_PER_SEC\|USECS_PER_SEC\|MSECS_PER_SEC\|USECS_PER_MSEC\|mono_time\|microseconds\|timeout_callback\|expiration\|timer_monotonic_get\|timers_run\|timer_sched_callback\|mono_time_set_usecs\|mono_time_set_msecs\|mono_time_add_usecs\|mono_time_add_msecs\|mono_time_cmp\|mono_time_after\|mono_time_before\|mono_time_diff_microseconds\|stopwatch\|stopwatch_init\|stopwatch_init_usecs_expire\|stopwatch_init_msecs_expire\|stopwatch_tick\|stopwatch_expired\|stopwatch_wait_until_expired\|stopwatch_duration_usecs\|stopwatch_duration_msecs\|wait_us\|wait_ms' -- src/) Change-Id: I9cc14b4b90989bd9ab1018e5863eece120f861c0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/lib: Remove unused <delay.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<" Change-Id: I6fb603a17534e3a1593cb421c618f8119933292a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-23ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki
Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23lib/Makefile.inc: Remove effect-free lineAngel Pons
Because of a typo, `bootblcok-y += rtc.c` does nothing. Drop it. Change-Id: Ife2ee152ab32ef23df5986c47bec490db592ab60 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56216 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-16Spell *Boot Guard* with a space for official spellingPaul Menzel
See for example Intel document *Secure the Network Infrastructure – Secure Boot Methodologies* [1]. Change all occurrences with the command below: $ git grep -l BootGuard | xargs sed -i 's/BootGuard/Boot Guard/g' [1]: https://builders.intel.com/docs/networkbuilders/secure-the-network-infrastructure-secure-boot-methodologies.pdf Change-Id: I69fb64b525fb4799bcb9d75624003c0d59b885b5 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15lib/cbfs: Disable cbfs_preload in romstage when VBOOT_STARTS_IN_ROMSTAGERaul E Rangel
Preloading files before vboot runs and using them after vboot has finished will result in the wrong files getting used. Disable cbfs_preload to avoid this behavior. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7698b481a73fb24eecf4c810ff8be8b6826528ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-15rules.h, thread.h, lib/cbfs: Add ENV_STAGE_SUPPORTS_COOPRaul E Rangel
This change consolidates the COOP rules. Co-op in theory works in all x86 stages now, but it hasn't been enabled yet. BUG=b:179699789 TEST=Boot guybrush to OS and verify preloads still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1197406d1d36391998b08e3076146bb2fff59d00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-13cbfs: Enable CBFS verification KconfigsJulius Werner
With the elimination of remaining non-verifying CBFS APIs in CB:59682, CBFS verification is now ready to be used in its simplest form, so enable the respective Kconfig options in menuconfig. Add a few more restrictions to the TOCTOU_SAFETY option for problems that haven't been solved yet, and transform a comment in cbfs.c into a die() to make sure we don't accidentally forget implementing it once vboot integration gets added. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ifeba5c962c943856ab79bc6c4cb90a60c1de4a60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-12-06cbfs: Remove deprecated APIsJulius Werner
This patch removes all remaining pieces of the old CBFS API, now that the last straggling use cases of it have been ported to the new one (meaning cbfs_map()/cbfs_load()/etc... see CB:39304 and CB:38421). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-12-03cbfs | tspi: Join hash calculation for verification and measurementJulius Werner
This patch moves the CBFS file measurement when CONFIG_TPM_MEASURED_BOOT is enabled from the lookup step into the code where a file is actually loaded or mapped from flash. This has the advantage that CBFS routines which just look up a file to inspect its metadata (e.g. cbfs_get_size()) do not cause the file to be measured twice. It also removes the existing inefficiency that files are loaded twice when measurement is enabled (once to measure and then again when they are used). When CBFS verification is enabled and uses the same hash algorithm as the TPM, we are even able to only hash the file a single time and use the result for both purposes. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I70d7066c6768195077f083c7ffdfa30d9182b2b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-03region: Rename rdev_readat_full to rdev_read_fullJulius Werner
The 'at' part of the name refers to starting to read from a specific offset, so it doesn't make sense for the 'full' version of the function. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I60d595f0cbd161df171eaa4a76c7a00b6377e2b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59820 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-30cbfs: Add unverified_area APIsJulius Werner
This patch adds a new ..._unverified_area_... group of functions to the cbfs_map/_load/_alloc() APIs. These functions can be used to access custom FMAP sections and are meant to replace the existing cbfs_locate_file_in_region(). The name is intended to highlight that accesses through this API will not be verified when CBFS_VERIFICATION is enabled and should always be treated as if they may return malicious data. (Due to laziness I'm not adding the combination of this API with the ..._type_... variant at this point, since it seems very unlikely that we'll ever have a use case for that. If we ever do, it should be easy to add later.) (Also remove the 'inline' from cbfs_file_hash_mismatch(). I'm not sure why I put it there in the first place, probably a bad copy&paste.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I402265900f7075aa0c2f58d812c67ea63ddf2900 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-17cbfs: Add helper functions to look up size and type of a fileJulius Werner
This patch adds cbfs_get_size() and cbfs_get_type() helper functions (and _ro_ variations) to look up the size or type of a CBFS file without loading it. Generally, use of these should be discouraged because that tends to mean that the file needs to be looked up more than once, and cbfs_alloc() or cbfs_type_load() are usually the more efficient alternative... but sometimes they're unavoidable, so we might as well offer them. Also remove the <cbfs_private.h> header which had already become sort of unnecessary with previous changes. cbfs_boot_lookup() is now exported in <cbfs.h> for use in inlines, but should not be used directly by other files (and is prefixed with an underscore to highlight that). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I8092d8f6e04bdfb4df6c626dc7d42b402fe0a8ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/59312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
2021-11-16src/lib/prog_loaders: Add preload_ramstageRaul E Rangel
This will enable preloading ramstage. By preloading the file into cbfs_cache we reduce boot time. BUG=b:179699789 TEST=Boot guybrush to OS and see 12ms reduction in boot time. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibe12de806449da25bc0033b02fcb97c3384eddc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-16lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preloadRaul E Rangel
Now that CBFS has this functionality built in, we no longer need to manually code it. payload_preload used to use the payload_preload_cache region to store the raw payload contents. This region was placed outside the firmware reserved region, so it was available for use by the OS. This was possible because the payload isn't loaded again on S3 resume. cbfs_preload only uses the cbfs_cache region. This region must be reserved because it gets used on the S3 resume path. Unfortunately this means that cbfs_cache must be increased to hold the payload. Cezanne is the only platform currently using payload_preload, and the size of cbfs_cache has already been adjusted. In the future we could look into adding an option to cbfs_preload that would allow it to use a different memory pool for the cache allocation. BUG=b:179699789 TEST=Boot guybrush and verify preloading the payload was successful CBFS DEBUG: get_preload_rdev(name='fallback/payload') preload successful Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-15lib/hardwaremain: Run timers more frequentlyRaul E Rangel
This change makes it so the timers run after each boot state callback, and after each boot state. This gives coop threads the opportunity to run more frequently and predictably. BUG=b:179699789 TEST=Boot guybrush to OS, see SPI transactions progress faster. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9508e7777d52fe934cc09d486abc0dab5cf7dad8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-11arch/x86: Refactor the SMBIOS type 17 write functionSubrata Banik
List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Use dedicated Memory Type and Module type for `Form Factor` and `TypeDetail` conversion using `get_spd_info()` function. 3. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 4. Add new argument as `Memory Type` to smbios_form_factor_to_spd_mod_type() so that it can internally call convert_form_factor_to_module_type() for `Module Type` conversion. 5. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. 6. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-10lib/thread: Start stopwatch after printkRaul E Rangel
We are currently counting how long it takes to print the waiting message, in addition to the actual time we spent waiting. This results in inflating the measurement by 1.7ms when the serial console is enabled. This CL makes it so the print happens before the stopwatch starts. BUG=b:179699789 TEST=No longer see printk time taken into account on serial console Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib48e37c1b2cb462d634141bf767673936aa2dd26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-08src/lib: Add FW_CONFIG_SOURCE_VPDWonkyu Kim
Read fw_config value from VPD. This new option can be used where chrome EC is not supported like pre-silicon platform and fw_config can be updated by VPD tool in OS. TEST= boot to OS and read fw_config from vpd 1. Boot to OS 2. Write "fw_config" in VPD ex) vpd -i "RW_VPD" -s "fw_config"="1" 3. reboot and check fw_config value from coreboot log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4df7d5612e18957416a40ab854fa63c8b11b4216 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-08src/lib/fw_config: Change fw_config sources priorityWonkyu Kim
Request fw_config values from various sources (as enabled via Kconfig) until a valid value has been read. With this change, Chrome EC CBI takes precedence over CBFS fw_config. TEST=select both configs and check fallback behavior. 1. select both FW_CONFIG_SOURCE_CHROMEEC_CBI and FW_CONFIG_SOURCE_CBFS 2. check log for reading fw_config from CBI and CBFS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I215c13a4fcb9dc3b94f73c770e704d4e353e9cff Reviewed-on: https://review.coreboot.org/c/coreboot/+/58833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04lib/cbfs: Add cbfs_preload()Raul E Rangel
This API will hide all the complexity of preloading a CBFS file. It makes it so the callers simply specify the file to preload and CBFS takes care of the rest. It will start a new thread to read the file into the cbfs_cache. When the file is actually required (i.e., cbfs_load, etc) it will wait for the preload thread to complete (if it hasn't already) and perform verification/decompression using the preloaded buffer. This design allows decompression/verification to happen in the main BSP thread so that timestamps are correctly reflected. BUG=b:179699789 TEST=Test with whole CL chain, verify VGA bios was preloaded and boot time was reduced by 12ms. Logs: Preloading VGA ROM CBFS DEBUG: _cbfs_preload(name='pci1002,1638.rom', force_ro=false) CBFS: Found 'pci1002,1638.rom' @0x20ac40 size 0xd800 in mcache @0xcb7dd0f0 spi_dma_readat_dma: start: dest: 0x021c0000, source: 0x51cc80, size: 55296 took 0 us to acquire mutex start_spi_dma_transaction: dest: 0x021c0000, source: 0x51cc80, remaining: 55296 ... spi_dma_readat_dma: end: dest: 0x021c0000, source: 0x51cc80, remaining: 0 ... CBFS DEBUG: _cbfs_alloc(name='pci1002,1638.rom', alloc=0x00000000(0x00000000), force_ro=false, type=-1) CBFS: Found 'pci1002,1638.rom' @0x20ac40 size 0xd800 in mcache @0xcb7dd0f0 waiting for thread took 0 us CBFS DEBUG: get_preload_rdev(name='pci1002,1638.rom', force_ro=false) preload successful In CBFS, ROM address for PCI: 03:00.0 = 0x021c0000 PCI expansion ROM, signature 0xaa55, INIT size 0xd800, data ptr 0x01b0 PCI ROM image, vendor ID 1002, device ID 1638, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from 0x021c0000 to 0xc0000, 0xd800 bytes $ cbmem ... 40:device configuration 5,399,404 (8,575) 65:Option ROM initialization 5,403,474 (4,070) 66:Option ROM copy done 5,403,488 (14) ... Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I879fc1316f97417a4b82483d353abdbd02b98a31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-04lib/thread: Use __func__ instead of repeating function nameRaul E Rangel
This cleans up the warning message: WARNING: Prefer using '"%s...", __func__' to using 'thread_run', this function's name, in a string BUG=b:179699789 TEST=boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I85bacb7b2d9ebec40b6b05edc2ecf0ca1fc8ceee Reviewed-on: https://review.coreboot.org/c/coreboot/+/58867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-04lib/thread: Add ERROR prefix to error messagesRaul E Rangel
This makes it easier to grep for errors. BUG=b:179699789 TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7eecdfed6046b7d609069e7427f6883a4e9e521d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-04lib: Add list.c to all stagesRaul E Rangel
This will be used in cbfs.c which is used in all stages. BUG=b:179699789 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0713ae766c0ac9e43de702690ad0ba961d636d18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-04lib/cbfs: Add CBFS_CACHE_ALIGN Kconfig optionRaul E Rangel
This option will allow platforms to set the alignment of the cbfs_cache buffers. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 8, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I74598d4bcbca9a01cc8c65012d7e4ae341d052b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-04commonlib/mem_pool: Allow configuring the alignmentRaul E Rangel
AMD platforms require the destination to be 64 byte aligned in order to use the SPI DMA controller. This is enforced by the destination address register because the first 6 bits are marked as reserved. This change adds an option to the mem_pool so the alignment can be configured. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56580 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03lib/list: Add list_appendRaul E Rangel
This method will add a node to the end of the list. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1792e40f789e3ef16ceca65ce4cae946e08583d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-02google/trogdor: Add backlight support for Parade ps8640xuxinxiong
Add backlight support in ps8640 through the AUX channel using eDP DPCD registers. BUG=b:202966352 BRANCH=trogdor TEST=verified firmware screen works on homestar rev4 Change-Id: Ief1bf56c89c8215427dcbddfc67e8bcd4c3607d2 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-02lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()Subrata Banik
Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-30lib: Use `smbios_bus_width_to_spd_width` for setting dimm.bus_widthSubrata Banik
Make use of `smbios_bus_width_to_spd_width()` for filling DIMM info. Additionally, ensures dimm_info_util.c file is getting compiled for romstage. TEST=dmidecode -t 17 output Total Width and Data Width as expected. Change-Id: I7fdc19fadc576dec43e12f182fe088707e6654d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29lib/cbfs: Enable cbfs_cache for x86Raul E Rangel
The reason cbfs_cache was disabled on x86 was due to the lack of .data sections in the pre-RAM stages. By using ENV_STAGE_HAS_DATA_SECTION we enable x86 to start using the cbfs_cache. We still need to add a cbfs_cache region into the memlayout for it to be enabled. BUG=b:179699789 TEST=Build guybrush and verify cbfs_cache.size == 0. Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I74434ef9250ff059e7587147b1456aeabbee33aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/56577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-27src/lib/fmap.c: use le*toh() functions where neededKrystian Hebel
FMAP was developed with assumption about endianness of the target machine. This broke the parsing of the structure on big endian architectures. This patch converts the endianness of the fields where applicable. Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: I8784ac29101531db757249496315f43e4008de4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-20lib/cbfs: Call rdev_unmap on hash mismatchRaul E Rangel
We don't want to leak any mappings. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibcd28ce12cbd5e221e8f4fa910fd8472bedb802f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-18arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/threadRaul E Rangel
We only ever start and execute threads on the BSP. By explicitly checking to see if the CPU is the BSP we can remove the dependency on cpu_info. With this change we can in theory enable threads in all stages. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and verify coop multithreading still works Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iea4622d52c36d529e100b7ea55f32c334acfdf3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58199 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-05lib/thread: Remove thread stack alignment requirementRaul E Rangel
CPU_INFO_V2 now encapsulates the cpu_info requirements. They no longer need to leak through to thread.c. This allows us to remove the alignment requirement. BUG=b:179699789 TEST=Reboot stress test guybrush 50 times. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0af91feddcbd93b7f7d0f17009034bd1868d5aef Reviewed-on: https://review.coreboot.org/c/coreboot/+/57928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05lib/thread: Switch to using CPU_INFO_V2Raul E Rangel
CPU_INFO_V2 changes the behavior of cpu_info(). There is now only 1 cpu_info struct per cpu. This means that we no longer need to allocate it at the top of each threads stack. We can now in theory remove the CONFIG_STACK_SIZE alignment on the thread stack sizes. We can also in theory use threads in SMM if you are feeling venturesome. BUG=b:194391185, b:179699789 TEST=Perform reboot stress test on guybrush with COOP_MULTITASKING enabled. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5e04d254a00db43714ec60ebed7c4aa90e23190a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05src/acpi to src/lib: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-04coreboot tables: Add type-c port info to coreboot tableNick Vaccaro
This change adds type-c port information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds successfully. Cherry-pick CL to enable this feature for volteer, flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04lib/hardwaremain: change type of "complete" element in boot_state structFelix Held
A signed bitfield with a length of 1 bit can only have the values 0 and -1. Assigning a 1 ends up behaving as expected, but it's not the semantically correct thing to do there. Changing the type of the element to an unsigned bitfield with a length of 1 would fix that, but since this is used as a boolean value, just change it to bool type. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I230804335e7a15a8a9489859b20846988ba6c5cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-04lib/hardwaremain: add missing types.h includeFelix Held
The u8 type is used in the file, but neither stdint.h not types.h was included in the file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd67aff9eba01f9618004c869f1473217b3aeae4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-23lib/Makefile.inc: Generate placeholder spd.bin in lib/Makefile.incReka Norman
When a new variant is created, it needs to have a path to its SPD binary defined. Currently, this is done by setting SPD_SOURCES to a placeholder SPD file, which just contains zero bytes. To remove the need for a placeholder file, automatically generate a single-byte spd.bin in lib/Makefile.inc when SPD_SOURCES is set to the marker value 'placeholder'. BUG=b:191776301 TEST=Change cappy/memory/Makefile to `SPD_SOURCES = placeholder`. Build and check that spd.bin contains a single zero byte. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I11f8f9b7ea3bc32aa5c7a617558572a5c1c74c72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21lib/Makefile.inc: Fail build if SPD file doesn't existReka Norman
Currently, if LIB_SPD_DEPS contains an SPD file which doesn't exist, the file is silently skipped when creating spd.bin. Instead, fail the build. BUG=b:191776301 TEST=Build test on brya. Build fails if a non-existent file is included in LIB_SPD_DEPS. Change-Id: I1bdadb72e087c2ee7a88fbab2f3607bd400fa2e4 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-04Move post_codes.h to commonlib/console/Ricardo Quesada
Move post_codes.h from include/console to commonlib/include/commonlib/console. This is because post_codes.h is needed by code from util/ (util/ code in different commit). Also, it sorts the #include statements in the files that were modified. BUG=b:172210863 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Change-Id: Ie48c4b1d01474237d007c47832613cf1d4a86ae1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56403 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26arch/x86,lib/thread: Enable thread support in romstageRaul E Rangel
This change does the following: * Pushes the cpu_info struct into the top of the stack (just like c_start.S). This is required so the cpu_info function works correctly. * Adds the thread.c to the romstage build. I only enabled this for romstage since I haven't done any tests in other stages, but in theory it should work for other stages. BUG=b:179699789 TEST=Boot guybrush with threads enabled in romstage Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8e32e1c54dea0d0c85dd6d6753147099aa54b9b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-26lib/thread,lib/hardwaremain: Lazy initialize threadsRaul E Rangel
By lazy initializing the threads, if a stage doesn't use them, they will be garbage collected. BUG=b:179699789 TEST=Boot guybrush to the OS and verify threads worked Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7208ffb5dcda63d916bc6cfdea28d92a62435da6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56532 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26lib/thread,arch/x86: Move thread stacks into C bssRaul E Rangel
There is no reason this needs to be done in asm. It also allows different stages to use threads. If threads are no used in a specific stage, the compiler will garbage collect the space. BUG=b:179699789 TEST=Boot guybrush to the OS Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib5a84a62fdc75db8ef0358ae16ff69c20cbafd5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56531 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26lib/thread: Add asserts around stack size and alignmentRaul E Rangel
`cpu_info()` requires that stacks be STACK_SIZE aligned and a power of 2. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I615623f05bfbe2861dcefe5cae66899aec306ba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-26lib/thread: Guard thread_run_until with ENV_RAMSTAGERaul E Rangel
thread_run_until is a ramstage specific API. This change guards the API by checking ENV_RAMSTAGE. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4784942070fd352a48c349f3b65f5a299abf2800 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56529 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-20lib/cbfs,device/pci_rom: Move cbfs_boot_map_optionrom and modernizeRaul E Rangel
These methods are oprom specific. Move them out of CBFS. I also deleted the tohex methods and replaced them with snprintf. BUG=b:179699789 TEST=Boot guybrush and see oprom still loads Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I03791f19c93fabfe62d9ecd4f9b4fad0e6a6146e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-19lib/prog_loaders: Add payload_preloadRaul E Rangel
This method will allow the SoC code to start loading the payload before it is required. BUG=b:177909625 TEST=Boot guybrush and see read/decompress drop by 23 ms. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifa8f30a0f4f931ece803c2e8e022e4d33d3fe581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-18lib/hardwaremain: Drop boot_state_current_{block,unblock}()Raul E Rangel
There are no more callers. BUG=b:179699789 TEST=Compile guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I522f17c0e450641c0a60496ba07800da7e39889c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56389 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18lib/thread: Make thread_run not block the current stateRaul E Rangel
If a thread wants to block a state transition it can use thread_run_until. Otherwise just let the thread run. `thread_join` can be used to block on the thread. Boot states are also a ramstage concept. If we want to use this API in any other stage, we need a way of starting a thread without talking about stages. BUG=b:179699789 TEST=verify thread_run no longer blocks the current state Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3e5b0aed70385ddcd23ffcf7b063f8ccb547fc05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56351 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18lib/thread: Add thread_handleRaul E Rangel
The thread_handle can be used to wait for a thread to exit. I also added a return value to the thread function that will be stored on the handle after it completes. This makes it easy for the callers to check if the thread completed successfully or had an error. The thread_join method uses the handle to block until the thread completes. BUG=b:179699789 TEST=See thread_handle state update and see error code set correctly. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie6f64d0c5a5acad4431a605f0b0b5100dc5358ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56229 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18lib/thread: Add mutexRaul E Rangel
We need a way to protect shared resources. Since we are using cooperative multitasking the mutex implementation is pretty trivial. BUG=b:179699789 TEST=Verify thread lock and unlock. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ife1ac95ec064ebcdd00fcaacec37a06ac52885ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56230 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18lib/thread: Rename thread_cooperate and thread_prevent_coopRaul E Rangel
Renaming them to thread_coop_disable()/thread_coop_enable() makes them sound like a pair. BUG=b:179699789 TEST=Boot guybrush to OS Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1d70c18965f53e733e871ca03107270612efa4fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/56357 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18lib/thread: Allow nesting thread_cooperate and thread_prevent_coopRaul E Rangel
This change allows nesting critical sections, and frees the caller from having to keep track of whether the thread has coop enabled. BUG=b:179699789 TEST=Boot guybrush with SPI DMA Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I325ab6181b17c5c084ca1e2c181b4df235020557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56350 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18lib/thread: Clean up initialization sequenceRaul E Rangel
idle_thread_init was actually configuring the BSP thread at the end. We can instead do this in threads_initialize. This now lets us set initialized after the idle thread has been set up. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7f1d6afac3b0622612565b37c61fbd2cd2481552 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56356 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18lib/thread: Add thread_yield helper methodRaul E Rangel
This helper method is just a shorthand for `thread_yield_microseconds(0)`. I think it makes it clear that we want to yield a thread without delaying. BUG=b:179699789 TEST=build test Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id8b60c35b183cff6871d7ba70b36eb33b136c735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56349 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15lib/thread: Verify threads are initialized before yieldingRaul E Rangel
In hardwaremain.c we call console_init before threads_initialize. Part of setting up the uart requires calling udelay which then calls thread_yield_microseconds. Since threads have not been set up, trying to yield will result in bad things happening. This change guards the thread methods by making current_thread return NULL if the structures have not been initialized. BUG=b:179699789 TEST=Ramstage no longer hangs with serial enabled Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If9e1eedfaebe584901d2937c8aa24e158706fa43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56318 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-02selfboot: Add support for selfload in romstageShelley Chen
Since bootmem is not available in romstage, calls to bootmem APIs need to be compile-time eliminated in order to avoid linker error: undefined reference to `bootmem_region_targets_type BUG=None BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B cherry-picked on top of CB:49392 and verified successful compilation. Change-Id: I8dfa2f2079a9a2859114c53c22bf7ef466ac2ad9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55865 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18nvs: Add Chrome OS NVS (CNVS) information to coreboot tablesFurquan Shaikh
CB:51638 separated Chrome OS NVS from global NVS by allocating it separately in CBMEM. CNVS is used in depthcharge to fill firmware information at boot time. Thus, location of CNVS needs to be shared in coreboot tables for depthcharge to use. This change adds a new coreboot table tag `CB_TAG_ACPI_CNVS`/`CB_TAG_ACPI_CNVS`(0x41) which provides the location of CNVS in CBMEM to payload (depthcharge). Additionally, CB:51639 refactored device nvs(DNVS) and moved it to the end of GNVS instead of the fixed offset 0x1000. DNVS is used on older Intel platforms like baytrail, braswell and broadwell and depthcharge fills this at boot time as well. Since DNVS is no longer used on any new platforms, this information is not passed in coreboot tables. Instead depthcharge is being updated to use statically defined offsets for DNVS. BUG=b:191324611, b:191324611 TEST=Verified that `crossystem fwid` which reads fwid information from CNVS is reported correctly on brya. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3815d5ecb5f0b534ead61836c2d275083e397ff0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55665 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14ChromeOS: Separate NVS from global GNVSKyösti Mälkki
Allocate chromeos_acpi in CBMEM separately from GNVS. Change-Id: Ide55964ed53ea1d5b3c1c4e3ebd67286b7d568e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14lib/hardwaremain: Print individual boot state callback durationsRaul E Rangel
This is useful when trying to find which callbacks are taking the longest time. BUG=b:179092979 TEST=See bootstate durations in logs BS: callback (0xcb79d4d8) @ src/security/vboot/bootmode.c:53 (0 ms). BS: callback (0xcb79cf20) @ src/vendorcode/google/chromeos/ramoops.c:30 (0 ms). BS: callback (0xcb79cef0) @ src/vendorcode/google/chromeos/cr50_enable_update.c:160 (18 ms). Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifb145fea32ad4e0b694bdb7cdcdd43dce4cc0d27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55374 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14lib/hardwaremain.c: Hide preprocessor guards in headerAngel Pons
The `location` member of `struct boot_state_callback` is conditionally guarded depending on `CONFIG(DEBUG_BOOT_STATE)` using preprocessor. It is probably intended to save some space when the `location` strings do not get printed. However, directly using the `location` member without any guards will cause a compile-time error. Plus, preprocessor-guarded code gets nasty really quickly. In order to minimise preprocessor usage, introduce the `bscb_location` inline helper function, which transforms the compile-time error into a link-time error. It is then possible to substitute preprocessor guards with an ordinary C `if` statement. Change-Id: I40b7f29f96ea96a5977b55760f0fcebf3a0df733 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-05-30drivers/pc80/mc146818rtc: Check date and time for sanityWerner Zeh
There are cases where the RTC_VRT bit in register D stays set after a power failure while the real date and time registers can contain rubbish values (can happen when RTC is not buffered). If we do not detect this invalid date and/or time here and keep it, Linux will use these bad values for the initial timekeeper init. This in turn can lead to dates before 1970 in user land which can break a lot assumptions. To fix this, check date and time sanity when the RTC is initialized and reset the values if needed. Change-Id: I5bc600c78bab50c70372600347f63156df127012 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54914 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30lib/rtc: Add sanity check for time and dateWerner Zeh
Add a function to check sanity of a given RTC date and time. Invalid values in terms of overrun ranges of the registers can lead to strange issues in the OS. Change-Id: I0a381d445c894eee4f82b50fe86dad22cc587605 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-27cbmem: Introduce "early" init hooks for consoleJulius Werner
Over the last couple of years we have continuously added more and more CBMEM init hooks related to different independent components. One disadvantage of the API is that it can not model any dependencies between the different hooks, and their order is essentially undefined (based on link order). For most hooks this is not a problem, and in fact it's probably not a bad thing to discourage implicit dependencies between unrelated components like this... but one resource the components obviously all share is CBMEM, and since many CBMEM init hooks are used to create new CBMEM areas, the arbitrary order means that the order of these areas becomes unpredictable. Generally code using CBMEM should not care where exactly an area is allocated, but one exception is the persistent CBMEM console which relies (on a best effort basis) on always getting allocated at the same address on every boot. This is, technically, a hack, but it's a pretty harmless hack that has served us reasonably well so far and would be difficult to realize in a more robust way (without adding a lot of new infrastructure). Most of the time, coreboot will allocate the same CBMEM areas in the same order with the same sizes on every boot, and this all kinda works out (and since it's only a debug console, we don't need to be afraid of the odd one-in-a-million edge case breaking it). But one reproducible difference we can have between boots is the vboot boot mode (e.g. normal vs. recovery boot), and we had just kinda gotten lucky in the past that we didn't have differences in CBMEM allocations in different boot modes. With the recent addition of the RW_MCACHE (which does not get allocated in recovery mode), this is no longer true, and as a result CBMEM consoles can no longer persist between normal and recovery modes. The somewhat kludgy but simple solution is to just create a new class of specifically "early" CBMEM init hooks that will always run before all the others. While arbitrarily partitioning hooks into "early" and "not early" without any precise definition of what these things mean may seem a bit haphazard, I think it will be good enough in practice for the very few cases where this matters and beats building anything much more complicated (FWIW Linux has been doing something similar for years with device suspend/resume ordering). Since the current use case only relates to CBMEM allocation ordering and you can only really be "first" if you allocate in romstage, the "early" hook is only available in romstage for now (could be expanded later if we find a use case for it). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If2c849a89f07a87d448ec1edbad4ce404afb0746 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-27lib/hexdump: remove hexdump32 and use hexdump insteadFelix Held
hexdump and hexdump32 do similar things, but hexdump32 is mostly a reimplementation that has additional support to configure the console log level, but has a very unexpected len parameter that isn't in bytes, but in DWORDs. With the move to hexdump() the console log level for the hexdump is changed to BIOS_DEBUG. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6138d17f0ce8e4a14f22d132bf5c64d0c343b80d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54925 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-24fw_config: Add helper function `fw_config_probe_dev`Furquan Shaikh
This change adds a helper function `fw_config_probe_dev()` that allows the caller to check if any of the probe conditions are true for any given device. If device has no probe conditions or a matching probe condition, then it returns true and provides the matching probe condition back to caller (if provided with a valid pointer). Else, it returns false. When fw_config support is disabled, this function always returns true. Change-Id: Ic2dae338e6fbd7755feb23ca86c50c42103f349b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54751 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-24fw_config: Return false in `fw_config_probe` in unprovisioned caseFurquan Shaikh
fw_config is unprovisioned in the factory for the first boot. This is the only case where fw_config is left unprovisioned. On first boot in factory, fw_config gets correctly provisioned by the factory toolkit. When fw_config is unprovisioned, it is not always possible to make a guess which device to enable/disable since there can be certain conflicting devices which can never be enabled at the same time. That is the reason the original implementation of fw_config library kept fw_config as 0 when it was unprovisioned. CB:47956 ("fw_config: Use UNDEFINED_FW_CONFIG to mean unprovisioned") added support for a special unprovisioned value to allow any callers to identify this factory boot condition and take any appropriate action required for this boot (Ideally, this would just involve configuring any boot devices essential to getting to OS. All other non-essential devices can be kept disabled until fw_config is properly provisioned). However, CB:47956 missed handling the `fw_config_probe()` function and resulted in silent change in behavior. This change fixes the regression introduced by CB:47956 and returns `false` in `fw_config_probe()` if fw_config is not provisioned yet. Change-Id: Ic22cd650d3eb3a6016fa2e2775ea8272405ee23b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54750 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14cbfs: Increase mcache size defaultsJulius Werner
The CBFS mcache size default was eyeballed to what should be "hopefully enough" for most users, but some recent Chrome OS devices have already hit the limit. Since most current (and probably all future) x86 chipsets likely have the CAR space to spare, let's just double the size default for all supporting chipsets right now so that we hopefully won't run into these issues again any time soon. The CBFS_MCACHE_RW_PERCENTAGE default for CHROMEOS was set to 25 under the assumption that Chrome OS images have historically always had a lot more files in their RO CBFS than the RW (because l10n assets were only in RO). Unfortunately, this has recently changed with the introduction of updateable assets. While hopefully not that many boards will need these, the whole idea is that you won't know whether you need them yet at the time the RO image is frozen, and mcache layout parameters cannot be changed in an RW update. So better to use the normal 50/50 split on Chrome OS devices going forward so we are prepared for the eventuality of needing RW assets again. The RW percentage should really also be menuconfig-controllable, because this is something the user may want to change on the fly depending on their payload requirements. Move the option to the vboot Kconfigs because it also kinda belongs there anyway and this makes it fit in better in menuconfig. (I haven't made the mcache size menuconfig-controllable because if anyone needs to increase this, they can just override the default in the chipset Kconfig for everyone using that chipset, under the assumption that all boards of that chipset have the same amount of available CAR space and there's no reason not to use up the available space. This seems more in line with how this would work on non-x86 platforms that define this directly in their memlayout.ld.) Also add explicit warnings to both options that they mustn't be changed in an RW update to an older RO image. BUG=b:187561710 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-05-12include/console: Rename and update POST_ENTRY_RAMSTAGE postcodeSubrata Banik
Rename and update POST_ENTRY_RAMSTAGE postcode value from 0x80 to 0x6f to make the ramstage postcodes appear in an incremental order. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba Reviewed-on: https://review.coreboot.org/c/coreboot/+/52947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-10src: Drop "This file is part of the coreboot project" linesAngel Pons
Commit 6b5bc77c9b22c398262ff3f4dae3e14904c57366 (treewide: Remove "this file is part of" lines) removed most of them, but missed some files. Change-Id: Ib8e7ab26a74b52f86d91faeba77df3331531763f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-06security/tpm: Add option to init TPM in bootblockArthur Heymans
When using a hardware assisted root of trust measurement, like Intel TXT/CBnT, the TPM init needs to happen inside the bootblock to form a proper chain of trust. Change-Id: Ifacba5d9ab19b47968b4f2ed5731ded4aac55022 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51923 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05lib/coreboot_table.c: Remove unnecessary CPP useArthur Heymans
Change-Id: Ib93617867b946e208c31275d55d380aab7e51a50 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23lib/espi_debug: Add espi_show_slave_peripheral_channel_configurationRaul E Rangel
Prints out the following: eSPI Slave Peripheral configuration: Peripheral Channel Maximum Read Request Size: 64 bytes Peripheral Channel Maximum Payload Size Selected: 64 bytes Peripheral Channel Maximum Payload Size Supported: 64 bytes Bus master: disabled Peripheral Channel: ready Peripheral Channel: enabled BUG=none TEST=boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7d598ee4f0f9d8ec0b37767e6a5a70288be2cb86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-21commonlib/region: Turn addrspace_32bit into a more official APIJulius Werner
We had the addrspace_32bit rdev in prog_loaders.c for a while to help represent memory ranges as an rdev, and we've found it useful for a couple of things that have nothing to do with program loading. This patch moves the concept straight into commonlib/region.c so it is no longer anchored in such a weird place, and easier to use in unit tests. Also expand the concept to the whole address space (there's no real need to restrict it to 32 bits in 64-bit environments) and introduce an rdev_chain_mem() helper function to make it a bit easier to use. Replace some direct uses of struct mem_region_device with this new API where it seems to make sense. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ie4c763b77f77d227768556a9528681d771a08dca Reviewed-on: https://review.coreboot.org/c/coreboot/+/52533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-19lib/rtc: Fix incomplete leap year macroJakub Czapiga
Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Found-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: Ic434c969141c67ce317a5db0c8805de02c84eb08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-15lib/rtc: Remove unnecessary year constraint in rtc_calc_weekdayJakub Czapiga
Algorithm used to calculate weekday is now based on Zeller's rule, so it does not need if statement constraining year to 1971 and later. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I25e2e6a1c9b2fb1ac2576e028b580db0ea474d37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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