| Age | Commit message (Collapse) | Author |
|---|
|
For a long time, second parameter 'stop' has been
ignored. The tested range is within 1 MiB above 'start'.
Change-Id: Icbf94cd6a651fbf0cd9aab97eb11f9b03f0c3c31
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48561
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Having some symmetry with <soc/nvs.h> now allows to reduce
the amount of gluelogic to determine the size and cbmc field
of struct global_nvs.
Since GNVS creation is now controlled by ACPI_SOC_NVS,
drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne
cannot have this selected until <soc/nvs.h> exists.
Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
|
|
For arch/x86 the realmode part has to be located within the same 64
KiB as the reset vector. Some older intel platforms also require 4 KiB
alignment for _start16bit.
To enforce the above, and to separate required parts of .text without
matching *(.text.*) rules in linker scripts, tag the pre-C environment
assembly code with section .init directive.
Description of .init section for ELF:
This section holds executable instructions that contribute to the
process initialization code. When a program starts to run, the
system arranges to execute the code in this section before calling the
main program entry point (called main for C programs).
Change-Id: If32518b1c19d08935727330314904b52a246af3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47599
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I1e63a419db92642df6b7956050c39540c2ae11d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48781
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We need this to happen prior to SMM module loader. If
there is some debugging output it's better they do not
appear in the middle of CPU bringup.
Change-Id: I45b4b5c0c5bf8bee258a465d1e364bfe98190e44
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Files under sb/ or soc/ should not have includes that tie those
directly to external components like ChromeEC os ChromeOS
vendorcode.
Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48765
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Implement the ACPI PPI interface as described in
"TCG PC Client Physical Presence Interface Specification" Version 1.3.
Add a new Kconfig that allows to use the full PPI instead of the stub
version compiled in.
This doesn't add code to execute the PPI request, as that's up to the
payload with graphical UI support.
Tested on GNU/Linux 5.6 using the sysfs interface at:
/sys/class/tpm/tpm0/ppi/
Change-Id: Ifffe1d9b715e2c37568e1b009e86c298025c89ac
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45568
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
For arch/arm[64], the offsets to board identification strings and
CONFIG_ROM_SIZE inside .id were never really used; it was only a
convenience to have the strings appear near the start of image.
Add the same strings in an uncompressed file in CBFS.
Change-Id: I35d3312336e9c66d657d2ca619cf30fd79e18fd4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47602
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently it's not possible to add multiple graphics driver into
one coreboot image. This patch series will fix this issue by providing
a single API that multiple graphics driver can use.
This is required for platforms that have two graphic cards, but
different graphic drivers, like Intel+Aspeed on server platforms or
Intel+Nvidia on consumer notebooks.
The goal is to remove duplicated fill_fb_framebuffer(), the advertisment
of multiple indepent framebuffers in coreboot tables, and better
runtime/build time graphic configuration options.
Replace set_vbe_mode_info_valid with fb_add_framebuffer_info or
fb_new_framebuffer_info_from_edid.
Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Currently, the option to cache DIMM SPD data in an FMAP region
is closely coupled to a single board (google/hatch) and requires
a custom FMAP to utilize.
Loosen this coupling by introducing a Kconfig option which adds
a correctly sized and aligned RW_SPD_CACHE region to the default FMAP.
Add a Kconfig option for the region name, replacing the existing hard-
coded instance in spd_cache.h. Change the inclusion of spd_cache.c to
use this new Kconfig, rather than the board-specific one currently used.
Lastly, have google/hatch select the new Kconfig when appropriate to
ensure no change in current functionality.
Test: build/boot WYVERN google/hatch variant with default FMAP, verify
FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log.
Also tested on an out-of-tree Purism board.
Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently it's not possible to add multiple graphics drivers into
one coreboot image. This patch series will fix this issue by providing
a single API that multiple graphics drivers can use.
This is required for platforms that have two graphic cards, but
different graphic drivers, like Intel+Aspeed on server platforms or
Intel+Nvidia on consumer notebooks.
The goal is to remove duplicated fill_fb_framebuffer(), the advertisment
of multiple independent framebuffers in coreboot tables, and better
runtime/build time graphic configuration options.
Replace all duplications of fill_fb_framebuffer and provide a single one
in edid_fill_fb.c. Should not change the current behaviour as still only
one graphic driver can be active at time.
Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39003
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prevent null-pointer access when passed as parameter.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ie712d040b1c2383dcc8884e5f779c3591ccf0163
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
A mainboard might want to configure some things differently when a
device is in an unprovisioned state. In the case when fw_config comes
from the Chromium EC, an unprovisioned device will not have a FW_CONFIG
tag in its CBI. This patch will set the fw_config value to
UNDEFINED_FW_CONFIG in the case of an error retrieving the value, as
well as adding a function, `fw_config_is_provisioned()` to indicate the
provisioning status.
BUG=none
TEST=remove fw_config from chromium EC CBI, add code to mainboard to
print return value of fw_config_is_provisioned() (`0`), add
fw_config back to CBI, run same test and see `1`.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib3046233667e97a5f78961fabacbeb3099b3d442
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47956
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently it's not possible to add multiple graphics driver into
one coreboot image. This patch series will fix this issue by providing
a single API that multiple graphics driver can use.
This is required for platforms that have two graphic cards, but
different graphic drivers, like Intel and Aspeed on server platforms or
Intel and Nvidia on consumer notebooks.
The goals are to remove duplicated fill_fb_framebuffer(), to advertise
multiple independent framebuffers in coreboot tables, and better
runtime/build time graphic configuration options.
Add an implementation in edid_fill_fb that supports registering
multiple framebuffers, each with its own configuration.
As the current code is only compiled for a single graphics driver
there's no change in functionality.
Change-Id: I7264c2ea2f72f36adfd26f26b00e3ce172133621
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This patch addresses the same problem as CB:48429, but hopefully this
time correctly. Since the mcache is not guaranteed to be available on
the first CBFS lookup for some special cases, we can no longer treat it
as a one-time fire-and-forget initialization. Instead, we test
cbd->mcache_size to check if the mcache has been initialized yet, and
keep trying on every lookup if we don't find it the first time.
Since the mcache is a hard requirement for TOCTOU safety, also make it
more clear in Kconfig that configurations known to do CBFS accesses
before CBMEM init are incompatbile with that, and make sure we die()
rather than do something unsafe if there's a case that Kconfig didn't
catch.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4e01e9a9905f7dcba14eaf05168495201ed5de60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This reverts commit b652aaef990cc3eb481dea7f8d4cc3eecd92ffa1. It was
dumb and didn't actually fix anything.
Change-Id: I074135dd12face1226105e0706c78ae8ecba18e0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
There have been a few issues with the new CBFS mcache code in stages
after romstage, where the mcache resides in CBMEM. In a few special
cases the stage may be doing a CBFS lookup before calling
cbmem_initialize(). To avoid breaking those cases, this patch makes the
CBFS code fall back to a lookup from flash if CBMEM hasn't been
reinitialized yet in those stages.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Icf6d1a1288cb243d0c4c893cc58251687e2873b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
The new CBFS stack will log messages for found files but leaves error
messages up to the caller. This patch adds appropriate generic error
messages to cbfs_lookup(), matching the behavior of the old CBFS stack
for not found files.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8cf44026accc03c466105d06683027caf1693ff0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This patch adds the first stage of the new CONFIG_CBFS_VERIFICATION
feature. It's not useful to end-users in this stage so it cannot be
selected in menuconfig (and should not be used other than for
development) yet. With this patch coreboot can verify the metadata hash
of the RO CBFS when it starts booting, but it does not verify individual
files yet. Likewise, verifying RW CBFSes with vboot is not yet
supported.
Verification is bootstrapped from a "metadata hash anchor" structure
that is embedded in the bootblock code and marked by a unique magic
number. This anchor contains both the CBFS metadata hash and a separate
hash for the FMAP which is required to find the primary CBFS. Both are
verified on first use in the bootblock (and halt the system on failure).
The CONFIG_TOCTOU_SAFETY option is also added for illustrative purposes
to show some paths that need to be different when full protection
against TOCTOU (time-of-check vs. time-of-use) attacks is desired. For
normal verification it is sufficient to check the FMAP and the CBFS
metadata hash only once in the bootblock -- for TOCTOU verification we
do the same, but we need to be extra careful that we do not re-read the
FMAP or any CBFS metadata in later stages. This is mostly achieved by
depending on the CBFS metadata cache and FMAP cache features, but we
allow for one edge case in case the RW CBFS metadata cache overflows
(which may happen during an RW update and could otherwise no longer be
fixed because mcache size is defined by RO code). This code is added to
demonstrate design intent but won't really matter until RW CBFS
verification can be supported.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8930434de55eb938b042fdada9aa90218c0b5a34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This patch introduces two new CBFS API functions which are equivalent to
cbfs_map() and cbfs_load(), respectively, with the difference that they
always operate on the read-only CBFS region ("COREBOOT" FMAP section).
Use it to replace some of the simple cases that needed to use
cbfs_locate_file_in_region().
Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39306
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Looks like the option is generally not compatible with
garbage collections.
Nothing gets inlined, for example is_smp_boot() no longer
evaluates to constant false and thus the symbols from
secondary.S would need to be present for the build to pass
even if we set SMP=n.
Also the addresses of relocatable ramstage are currently
not normalised on the logs, so util/genprof would be unable
dress those.
Change-Id: I0b6f310e15e6f4992cd054d288903fea8390e5cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This patch adapts cbfs_load() and cbfs_map() to use the new CBFS API
directly, rather than through cbfs_boot_locate(). For cbfs_load() this
means that attribute metadata does not need to be read twice.
Change-Id: I754cc34b1c1471129e15475aa0f1891e02439a02
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file()
to cbfs_map() and cbfs_load() respectively. This is supposed to be the
start of a new, better organized CBFS API where the most common
operations have the most simple and straight-forward names. Less
commonly used variants of these operations (e.g. cbfs_ro_load() or
cbfs_region_load()) can be introduced later. It seems unnecessary to
keep carrying around "boot" in the names of most CBFS APIs if the vast
majority of accesses go to the boot CBFS (instead, more unusual
operations should have longer names that describe how they diverge from
the common ones).
cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly
reap mappings when desired. A few new cbfs_unmap() calls are added to
generic code where it makes sense, but it seems unnecessary to introduce
this everywhere in platform or architecture specific code where the boot
medium is known to be memory-mapped anyway. In fact, even for
non-memory-mapped platforms, sometimes leaking a mapping to the CBFS
cache is a much cleaner solution than jumping through hoops to provide
some other storage for some long-lived file object, and it shouldn't be
outright forbidden when it makes sense.
Additionally, remove the type arguments from these function signatures.
The goal is to eventually remove type arguments for lookup from the
whole CBFS API. Filenames already uniquely identify CBFS files. The type
field is just informational, and there should be APIs to allow callers
to check it when desired, but it's not clear what we gain from forcing
this as a parameter into every single CBFS access when the vast majority
of the time it provides no additional value and is just clutter.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
cbfs_boot_locate() is supposed to be deprecated eventually, after slowly
migrating all APIs to bypass it. That means common features (like
RO-fallback or measurement) need to be moved to the new
cbfs_boot_lookup().
Also export the function externally. Since it is a low-level API and
most code should use the higher-level loading or mapping functions
instead, put it into a new <cbfs_private.h> to raise the mental barrier
for using this API (this will make more sense once cbfs_boot_locate() is
removed from <cbfs.h>).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4bc9b7cbc42a4211d806a3e3389abab7f589a25a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is
enabled by default. Some older chipsets with insufficient SRAM/CAR space
still have it explicitly disabled. All others get the new section added
to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: Ia713e7dbe8c75b764f7a4ef1a029e64fb2d321fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This patch adds a new CBFS "mcache" (metadata cache) -- a memory buffer
that stores the headers of all CBFS files. Similar to the existing FMAP
cache, this cache should reduce the amount of SPI accesses we need to do
every boot: rather than having to re-read all CBFS headers from SPI
flash every time we're looking for a file, we can just walk the same
list in this in-memory copy and finally use it to directly access the
flash at the right position for the file data.
This patch adds the code to support the cache but doesn't enable it on
any platform. The next one will turn it on by default.
Change-Id: I5b1084bfdad1c6ab0ee1b143ed8dd796827f4c65
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
It was supposed to return true for both S2 and S3, but
level S2 was never stored in acpi_slp_type or otherwise
implemented.
Change-Id: Ida0165e647545069c0d42d38b9f45a95e78dacbe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
"printk()" needs <console/console.h>.
Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
While Ada makes pointers harder to use, it is still useful to provide a
pointer type for use in C interfaces.
Change-Id: I3a30ef0147a459ba82c79a1f85a3d3fb97b0f3a1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47393
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is a trivial patch to fix some comments that were generating
notes in the kconfig lint test.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I26a95f17e82910f50c62215be5c29780fe98e29a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47366
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There are currently 3 different strapping ID entries in the coreboot
table, which adds overhead. The new fw_config field is also desired in
the coreboot table, which is another kind of strapping id. Therefore,
this patch deprecates the 3 current strapping ID entries (board ID, RAM
code, and SKU ID), and adds a new entry ("board_config") which provides
board ID, RAM code, SKU ID, as well as FW_CONFIG together.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1ecec847ee77b72233587c1ad7f124e2027470bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Further patches will make use of this raw 64-bit value.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I161893c09da6a44265299f6ae3c3a81249a96084
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46604
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We all knew this was coming, 32 bits is never enough. Doing this early
so that it doesn't affect too much code yet. Take care of every usage of
fw_config throughout the codebase so the conversion is all done at once.
BUG=b:169668368
TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG
and verify the console print contained that bit.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch hooks coreboot up to the new commonlib/bsd CBFS
implementation. This is intended as the "minimum viable patch" that
makes the new implementation useable with the smallest amount of changes
-- that is why some of this may look a bit roundabout (returning the
whole metadata for a file but then just using that to fill out the rdevs
of the existing struct cbfsf). Future changes will migrate the higher
level CBFS APIs one-by-one to use the new implementation directly
(rather than translated into the results of the old one), at which point
this will become more efficient.
Change-Id: I4d112d1239475920de2d872dac179c245275038d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38422
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
EDID parser internal flag c->has_name_descriptor
was never set. It was causing decode_edid() function
to return NON_CONFORMANT instead of CONFORMANT even when
EDID frame was correct.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ifdc723b892a0885cfca08dab1a5ef961463da289
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
SMMSTORE version 2 is a complete redesign of the current driver. It is
not backwards-compatible with version 1, and only one version can be
used at a time.
Key features:
* Uses a fixed communication buffer instead of writing to arbitrary
memory addresses provided by untrusted ring0 code.
* Gives the caller full control over the used data format.
* Splits the store into smaller chunks to allow fault tolerant updates.
* Doesn't provide feedback about the actual read/written bytes, just
returns error or success in registers.
* Returns an error if the requested operation would overflow the
communication buffer.
Separate the SMMSTORE into 64 KiB blocks that can individually be
read/written/erased. To be used by payloads that implement a
FaultTolerant Variable store like TianoCore.
The implementation has been tested against EDK2 master.
An example EDK2 implementation can be found here:
https://github.com/9elements/edk2-1/commit/eb1127744a3a5d5c8ac4e8eb76f07e79c736dbe2
Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Make IMD private structures definitions accessible by other units.
To test IMD API correctness there is a need to access its internal
structure. It is only possible when private implementation is visible
in testing scope.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Iff87cc1990426bee6ac3cc1dfa6f85a787334976
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
cbfstool emits cbfs_stage objects in little endian encoding.
However, big endian targets then read the wrong values from
these objects. To maintain backwards compatibility with existing
cbfs objects add in the little endian deserialization.
Change-Id: Ia113f7ddfa93f0ba5a76e0397f06f9b84c833727
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Marty E. Plummer <hanetzer@startmail.com>
|
|
Currently, trogdor devices have a section RO_DDR_TRAINING that is used
to store memory training data. Changing so that we reuse the same
mrc_cache API as x86 platforms. This requires renaming
RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the
fmap table.
BUG=b:150502246
BRANCH=None
TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage
Make sure that first boot after flashing does memory training
and next boot does not.
Boot into recovery two consecutive times and make sure memory
training occurs on both boots.
Change-Id: I16d429119563707123d538738348c7c4985b7b52
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
The BIOS log was looking in the spd data for the part name, but part
names are stripped from generic SPDs. For these cases, a mainboard
can override the dram part number string, so the spd logging code
needs to check for an override string when logging the dram part
number.
Change print_spd_info() to use an override string if declared.
BUG=b:168724473
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer2 and verify that the BIOS log shows a part name when
logging SPD information:
SPD: module part number is K4U6E3S4AA-MGCL
I also modified volteer to not override the part name and verified
that this change did as expected and printed a blank string.
Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45459
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Make boot state init run before the init_chips code. This allows for
correcting tbt settings at a stage earlier than devicetree parsing.
BUG=b:167983038
TEST=none
Change-Id: I8364746ba311575e7de93fa25241ffef7faf35b4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45961
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add case for LPDDR4x to spd_get_name().
BUG=b:169800932, b:168724473
TEST=none
Change-Id: I6bae373468b8ad5ae0a6b8dd6bbe14143afb85af
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45886
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Consolidate all weak declarations of mainboard_get_dram_part_num() to
instead use the common definition in lib/spd_bin.c.
BUG=b:168724473
TEST="emerge-volteer coreboot && emerge-nocturne coreboot &&
emerge-dedede coreboot" and verify build succeeds without error.
Change-Id: I322899c080ab7ebcf1cdcad3ce3dfa1d022864d1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The coreboot toolchain has been using a newer GCC version for a while
already. This code is build-tested from commit 13cd145e02e onwards.
Change-Id: Ic324b503878c73e4560d4d8f2e0d38ecb595b8fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45822
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The config string is HAVE_SPD_IN_CBFS, without the "BIN".
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I728f64b2dd93b0e3947983b9b3701e185feff571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I56d13540b2c6b66d5c674ae3d5bab0ac9505df58
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45154
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a check to be sure that at least one SPD file will be added and fail
the build when the resulting spd.bin would be empty.
Change-Id: Ic6db1dbe5fed5f242e408bcad4f36dda1b1fa1b4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45131
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The name GENERIC_SPD_BIN doesn't reflect anymore what that config is
used for, so rename it to HAVE_SPD_BIN_IN_CBFS.
Change-Id: I4004c48da205949e05101039abd4cf32666787df
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
bootblock_main_with_timestamp function allows to proceed with existing
timestamp table. Apparently we never needed this, but Zork runs verstage
in the PSP before bootblock.
It'd be useful if we can grab timestamps for verstage from PSP and
merge with coreboot timestamps. Making it non-static will enable us to
do that.
BUG=b:154142138, b:159220781
BRANCH=zork
TEST=build firmware for zork
Change-Id: I061c3fbb652c40bafa0a007aa75f2a82680f5e0a
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Verstage in PSP used stub for timestamps since we didn't know about
clock. Now we figured out clock source so we can enable timestamp
functions.
BRANCH=zork
BUG=b:154142138, b:159220781
TEST=build without CONFIG_PSP_VERSTAGE_FILE, flash and boot
Change-Id: I431a243878e265b68783f54ee9424bb1d4fe03c1
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add region_file_update_data_arr, which has the same functionality as
region_file_update_data, but accepts mutliple data buffers. This is
useful for when we have the mrc_metadata and data in non-contiguous
addresses, which is the case when we bypass the storing of mrc_cache
data into the cbmem.
BUG=b:150502246
BRANCH=None
TEST=reboot from ec console. Make sure memory training happens.
reboot from ec console. Make sure that we don't do training again.
Change-Id: Ia530f7d428b9b07ce3a73e348016038d9daf4c15
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45407
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add check in setup_preram_cache to return if ENV_SMM is true.
This avoids false warning that post-RAM FMAP is accessed too early
caused by ENV_ROMSTAGE_OR_BEFORE evaluation in SMI handler.
BUG=b:167321319
BRANCH=None
TEST=None
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: I3a4c199c42ee556187d6c4277e8793a36e4d493b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This fixes the hex-to-bin conversion command, used to generated binary
SPD files from hexdumps.
An issue that only appeared on one of my systems, where conversion of
'01 02 03' to binary resulted in \x01\x32\x03 instead of \x01\x02\x03:
for c in 01 02 03; do printf $(printf '\%o' 0x$c); done | xxd -g 1
00000000: 01 32 03 .2.
The reason for this was that the syntax in lib/Makefile.inc is wrong,
because the backslash must be escaped due to chaining two printf
commands.
Change-Id: I36b0efac81977e95d3cc4f189c3ae418379fe315
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
SMBus code is linked unconditionally since commit 0e3c59e. This change
drops that obsolete part from the help text.
Change-Id: I603ab012760684021be1b5eca5d0ddff69463b79
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add a backing cache for all successfully probed fw_config fields that
originated as `probe` statements in the devicetree. This allows recall
of the `struct fw_config` which was probed.
BUG=b:161963281
TEST=tested with follower patch
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0d014206a4ee6cc7592e12e704a7708652330eaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
It seems that GCC's LTO doesn't like the way we implement
DECLARE_OPTIONAL_REGION(). This patch changes it so that rather than
having a normal DECLARE_REGION() in <symbols.h> and then an extra
DECLARE_OPTIONAL_REGION() in the C file using it, you just say
DECLARE_OPTIONAL_REGION() directly in <symbols.h> (in place and instead
of the usual DECLARE_REGION()). This basically looks the same way in the
resulting object file but somehow LTO seems to like it better.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6096207b311d70c8e9956cd9406bec45be04a4a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Removing entry covering root region leads to situation where
num_entries counter is set to 0. This counter is further decremented
in function obtaining address to last entry (see root_last_entry()).
Such negative number may be further used as an index to the table.
Current implementation may lead to crash, when user removes last entry
with imd_entry_remove() and then calls for example imd_entry_add().
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I6ff54cce55bf10c82a5093f47c7f788fd7c12d3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
One of the checks inside imdr_recover() was written with the
assumption that imdr limit is always aligned to LIMIT_ALIGN. This is
true only for large allocations, thus may fail for small regions.
It's not necessary to check if root_pointer is under the limit, since
this is implicitly verified by imdr_get_root_pointer().
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I25d6291301797d10c6a267b5f6e56ac38b995b7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
Previously it was allowed to create an imd_entry with size 0, however
algorithm sets the offset of such entry to the exact same address as
the last registered entry.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: Ifa2cdc887381fb0d268e2c199e868b038aafff5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
Add a check that root_size provided by the caller accounts for one
imd_entry necessary for covering imd_root region. Without this, we
may end up with writing on unallocated memory.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I0a39d56f7a2a6fa026d259c5b5b78def4f115095
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I8261c7d933435ba9f29fc3172cdfe8bcae5c1af9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
Get rid of the second check whether r is NULL (this is already done by imdr_has_entry()).
Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: Ibee1664ee45b29d36e2eaaa7dff4c7cc1942010b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
Remove the repetition from the comment.
Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: Ibe6e38636b96b6d8af702b05a822995fd576b2fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44662
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The assumption was that the fmap cache would be initialized in
bootblock, otherwise an error is shown. This error is showing
up in psp_verstage when the fmap cache is initialized there, so
create a new ENV value for ENV_INITIAL_STAGE.
BUG=None
TEST=Boot, see that error message is gone from psp_verstage
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I142f2092ade7b4327780d423d121728bfbdab247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43488
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Compiler's instrumentation cannot insert asan memory checks in
case of memory functions like memset, memcpy and memmove as they
are written in assembly.
So, we need to manually check the memory state before performing
each of these operations to ensure that ASan is triggered in case
of bad access.
Change-Id: I2030437636c77aea7cccda8efe050df4b77c15c7
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
This patch adds ASan support to romstage on x86 architecture.
A Kconfig option is added to enable ASan in romstage. Compiler
flags are updated. A memory space representing the shadow region
is reserved in linker section. And a function call to asan_init()
is added to initialize shadow region when romstage loads.
Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
This patch adds address sanitizer module to the library and reserves
a linker section representing the shadow region for ramstage. Also,
it adds an instruction to initialize shadow region on x86
architecture when ramstage is loaded.
Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
An additional compiler flag is added to make use of the shadow
offset callback feature we introduced in our GCC patch. Also,
a comment is added to tell user that this GCC patch needs to be
applied in order to use ASan.
Change-Id: Ia187e4991bf808f4ae137eff0ffdb9baea0085e9
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Add a Kconfig option to enable address sanitizer on x86 architecture.
Create ASan dummy functions. And add relevant gcc flags to compile
ramstage with ASan.
Change-Id: I6d87e48b6786f02dd46ea74e702f294082fd8891
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Change-Id: Iae1e875b466f8a195653d897efa1b297c61ad0a5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41912
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This can be used in romstage in particular to know if dram is ready.
Change-Id: I0231ab9c0b78a69faa762e0a97378bf0b50eebaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
People who know a lot more about electrons and stuff than I do tell me
that leaving a HiZ pin floating without a pull resistor may waste power.
So if we find a pin to be HiZ when reading tristate strapping GPIOs, we
should make sure the internal pull-down is enabled when we're done with
it. (For pins that are externally pulled high or low, we should continue
to leave the internal pull disabled instead.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1669823c8a7faab536e0441cb4c6cfeb9f696189
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44253
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Alexandru Stan <amstan@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Remove const struct imd *imd and const struct imdr *imdr parameters from
the prototypes of imdr_entry_size(), imd_entry_size() and imd_entry_id()
functions since they are not used anywhere.
Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: I6b43e9a5ae1f1d108024b4060a04c57f5d77fb55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43999
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This follows CB:44047 which probably missed this because it's a
custom assert macro (in code that has only recently been added to
build checks). Without this change, building with gcov fails because
gcc_assert(0) can be build-time verified (as introduced by CB:44044)
while we need runtime failure semantics here.
Change-Id: I71a38631955a6a45abe90f2b9ce3a924cc5d6837
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Adding implementation of standard library strstr()
See https://review.coreboot.org/c/coreboot/+/43741 for context.
Change-Id: I63e26e98ed2dd15542f81c0a3a5e353bb93b7350
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Looks like UBSan isn't being build-tested, and the toolchain has been
updated several times since UBSan support was added. Unexpectedly, it
no longer builds when using GCC from the current toolchain version.
To fix this, rename an error handler and add a newly-introduced handler
for `__ubsan_handle_pointer_overflow`, which works like the existing
handlers. A config file to allow build-testing UBSan is added later.
Change-Id: I5980730d8d22fa1d0512846c203004723847cc6d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Since regions in bootmem are sorted by increasing base address, we may
bail out of the search loop as soon as the region_base is bigger than
the max address allowed.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I44b44bf9618fd0615103cbf74271235d61d49473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43512
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is already defined in <commonlib/helpers.h> and it gets included
implicitly by some other header. Fixes building with code coverage.
Change-Id: Id2dc6cc34b6f1d351d8e1b52d8cc4ada8666c673
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Remove the obscure path in source code, where ACPI S3 resume
was prohibited and acpi_resume() would return and continue
to BS_WRITE_TABLES.
The condition when ACPI S3 would be prohibited needs to be
checked early in romstage already. For the time being, there
has been little interest to have CMOS option to disable
ACPI S3 resume feature.
Change-Id: If5105912759427f94f84d46d1a3141aa75cbd6ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Files found using:
diff <(git grep -l '#include <types.h>' -- src/) <(git grep -l 'BIT(\|size_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\|MAYBE_STATIC_NONZERO\|zeroptr\|int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|bool\|true\|false\|cb_err\|CB_SUCCESS\|CB_ERR\|CB_ERR_ARG\|CB_CMOS_\|CB_KBD_\|CB_I2C_\|cb_err_t\|DIV_ROUND_CLOSEST\|container_of\|__unused\|alloca(\|ARRAY_SIZE\|ALIGN\|ALIGN_UP\|ALIGN_DOWN\|IS_ALIGNED\|__CMP_UNSAFE\|MIN_UNSAFE\|MAX_UNSAFE\|__CMP_SAFE\|__CMP\|MIN(\|MAX(\|ABS(\|IS_POWER_OF_2\|POWER_OF_2\|DIV_ROUND_UP\|SWAP(\|KiB\|MiB\|GiB\|KHz\|MHz\|GHz\|offsetof(\|check_member\|member_size' -- src/)|grep -v vendor |grep '<'
Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41677
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Get rid of duplicated "if" statement in imdr_create_empty().
Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: I80c074d09f222086092478f8fd3ac665235ebb31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I379166c330d91c41846ba6562207fe5ad660040d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
|
|
The timestamp functionality is not yet added for psp_verstage, so
temporarily remove it until that's completed. That work is being
tracked by bug 154142138.
BUG=b:154142138
TEST=Build & Boot psp_verstage on trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I020619e3615ce92dedbe868104d2bfd83cb7caa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42381
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
A regression sneaked in with 18a8ba41cc (arch/x86: Remove RELOCATABLE_
RAMSTAGE). We want to call load_relocatable_ramstage() on x86, and
cbfs_prog_stage_load() on other architectures. But with the current
code the latter is also called on x86 if the former succeeded. Fix
that and also balance the if structure to make it more obvious.
TEST=qemu-system-x86_64 boots to payload again.
Change-Id: I5b1db5aac772b9b3a388a1a8ae490fa627334320
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43142
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We always have it, no need to support opting-out.
For PLATFORM_HAS_DRAM_CLEAR there is a dependency of ramstage
located inside CBMEM, which is only true with ARCH_X86.
Change-Id: I5cbf4063c69571db92de2d321c14d30c272e8098
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43014
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a new LB_TAG_PLATFORM_BLOB_VERSION for FSP version, it would
add Intel FSP version to coreboot table LB_TAG_PLATFORM_BLOB_VERSION
when PLATFORM_USES_FSP2_0 is selected.
Tested=On OCP Delta Lake, with an updated LinuxBoot payload cbmem utility
can see "LB_TAG_PLATFORM_BLOB_VERSION": "2.1-0.0.1.120"
Change-Id: I92a13ca91b9f66a7517cfd6784f3f692ff34e765
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Header was moved outside arch/.
Change-Id: I1f2f0d96d49b5d921f77512ad5e2bf3f60adb484
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Header and implementation only present for ARCH_X86 stages.
Change-Id: I4b28e666a8a60bd0365cda8d7affa1eb063c4690
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42416
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Once we support building stages for different architectures,
such CONFIG(ARCH_xx) tests do not evaluate correctly anymore.
Change-Id: I599995b3ed5c4dfd578c87067fe8bfc8c75b9d43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42183
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I39b8dc37219195e88ea6396aa7e987e5e244bbab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Once we support building stages for different architectures,
such CONFIG(ARCH_xx) tests do not evaluate correctly anymore.
For x86 we define .id linking explicitly elsewhere.
Change-Id: I43f849465e985068cd0b8a1944213b7c26245b8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This change introduces a new top-level interface for interacting with a
bitmask providing firmware configuration information.
This is motivated by Chromebook mainboards that need to support multiple
different configurations at runtime with the same BIOS. In these
devices the Embedded Controller provides a bitmask that can be broken
down into different fields and each field can then be broken down into
different options.
The firmware configuration value could also be stored in CBFS and this
interface will look in CBFS first to allow the Embedded Controller value
to be overridden.
The firmware configuration interface is intended to easily integrate
into devicetree.cb and lead to less code duplication for new mainboards
that make use of this feature.
BUG=b:147462631
TEST=this provides a new interface that is tested in subsequent commits
Change-Id: I1e889c235a81545e2ec0e3a34dfa750ac828a330
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Matching the same behavior change in depthcharge's FIT image code
(CL:2212466), this patch changes the order in which compat strings
involving revision and SKU numbers are matched when looking for a
compatible device tree. The most precise match (board-revX-skuY) is
still the highest priority, but after that we will now first check for
revision only (board-revX) and then for SKU only (board-skuY). The
reason for this is that SKU differentiation is often added later to a
project, so device trees for earlier revisions may not have SKU numbers
defined. So if we have a rev0 board (with sku0 as the "default SKU",
because the board only started having different SKUs with rev1) we want
it to match the board-rev0 device tree, not board-sku0 which was added
as an alias to board-rev1-sku0 to provide the best known default for
potential later revisions of that SKU.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia3cf7cbb165170e2ab0bba633fec01f9f509b874
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Allow the ability for chipset or mainboard to choose to
compress FSP-M in cbfs using LZMA or LZ4 routines. However, only
non-XIP platforms will support FSP-M compression. Since the main
cbfs decompression paths are utilized add the appropriate checks
for including compression algorithms under the FSP-M compression
options.
On picasso FSP-M (debug builds) the following savings were measured:
no-compression:
fspm.bin 720896 none
FSP_COMPRESS_FSP_M_LZ4:
fspm.bin 138379 LZ4 (720896 decompressed) -80%
FSP_COMPRESS_FSP_M_LZMA:
fspm.bin 98921 LZMA (720896 decompressed) -86%
BUG=b:155322763,b:150746858,b:152909132
Change-Id: I5c88510c134b56a36ff1cd97a64b51ab2fea0ab0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Allow the ability for chipset or mainboard to choose to
compress FSP-S in cbfs using LZMA or LZ4 routines. To accomplish
this fsp_load_component() is added as an assist for performing
the necessary logic and allow the caller to provide the destination
selection. Since the main cbfs decompression paths are utilized add
the appropriate checks for including compression algorithms under
the FSP-S compression options.
On picasso FSP-S (debug builds) the following savings were measured:
no-compression:
fsps.bin 327680 none
FSP_COMPRESS_FSP_S_LZ4:
fsps.bin 98339 LZ4 (327680 decompressed) -70%
FSP_COMPRESS_FSP_S_LZMA:
fsps.bin 71275 LZMA (327680 decompressed) -78%
BUG=b:155322763,b:150746858,b:152909132
Change-Id: I8aa5d8c1cbaf4d08f38a918a9031a2570bc5247e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The LZ4 compressed stages assume in-place decompression. The constraints
are validated in cbfstool for _stages_ such that they can be decompressed
in place. However, that is only true for stages. As such, add a wrapper,
cbfs_stage_load_and_decompress(), that handles the LZ4 stage loading case.
BUG=b:155322763,b:150746858,b:152909132
Change-Id: I9525a266250aa6c775283b598c09d4f40692db55
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41755
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add strtok() and strtok_r() to the library.
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Change-Id: Ic855b31669be1c274cbf247c53ffa6f74ec5bf35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
The sections .rom.* were for romcc and no longer used.
Some romcc comments were left behind when guards were removed.
Change-Id: I060ad7af2f03c67946f9796e625c072b887280c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
