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2014-03-20rmodules: use rmodtool to create rmodulesAaron Durbin
Start using the rmodtool for generating rmodules. rmodule_link() has been changed to create 2 rules: one for the passed in <name>, the other for creating <name>.rmod which is an ELF file in the format of an rmodule. Since the header is not compiled and linked together with an rmodule there needs to be a way of marking which symbol is the entry point. __rmodule_entry is the symbol used for knowing the entry point. There was a little churn in SMM modules to ensure an rmodule entry point symbol takes a single argument. Change-Id: Ie452ed866f6596bf13f137f5b832faa39f48d26e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5379 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-03-11chromeos: provide option to dynamically allocate ram oops bufferAaron Durbin
Fixing the location of the ram oops buffer can lead to certain kernel and boot loaders being confused when there is a ram reservation low in the address space. Alternatively provide a mechanism to allocate the ram oops buffer in cbmem. As cbmem is usually high in the address space it avoids low reservation confusion. The patch uncondtionally provides a GOOG9999 ACPI device with a single memory resource describing the memory region used for the ramoops region. BUG=None BRANCH=baytrail,haswell TEST=Built and booted with and w/o dynamic ram oops. With the corresponding kernel change things behave correctly. Change-Id: Ide2bb4434768c9f9b90e125adae4324cb1d2d073 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5257 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11rmodule: allow rmodule header structure to be used by userlandAaron Durbin
In order for userland to create rmodules the common code should be shareable. Therefore, convert the short u<width> name types to the posix uint<width>_t types. Additionally, move the definition of the header structure to a new rmodule-defs.h header file so that userland can include that without pulling in the coreboot state. Change-Id: I54acd3bfd8c207b9efd50a3b6d89efd5fcbfc1d9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5363 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-08lib/dynamic_cbmem.c: Include `cbmem_console.h`Paul Menzel
Broken with commit 1d7541fe (console: Fix includes). Change-Id: If41f9e08df98d79b7bbf740b1a5634d0140207be Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5351 Tested-by: build bot (Jenkins)
2014-03-07x86: add MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING optionAaron Durbin
Boot speeds can be sped up by mirroring the payload into main memory before doing the actual loading. Systems that would benefit from this are typically Intel ones whose SPI are memory mapped. Without the SPI being cached all accesses to the payload in SPI while being loaded result in uncacheable accesses. Instead take advantage of the on-board SPI controller which has an internal cache and prefetcher by copying 64-byte cachelines using 32-bit word copies. Change-Id: I4aac856b1b5130fa2d68a6c45a96cfeead472a52 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5305 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-04Add a generic register script handlerDuncan Laurie
This is based on the RCBA configuration setup from haswell. It handles PCI, BARs, IO, MMIO, and baytrail-specific IOSF. I did not extend it to handle MSR yet but that would be another potential register type. There are a number of approaches to this kind of thing, but in the end they have a lot of switch statements and a mass of #defines. I'm not particularly set on any of the details so comments welcome. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Ib873936ecf20fc996a8feeb72b9d04ddb523211f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175206 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4923 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04usbdebug: Move Kconfig under drivers/usbKyösti Mälkki
This menu may become a bit more complicated with addition of new USB hardware so move it out of console/. Change-Id: Ieb330675b9227a3e53d093f7c2b5a65e3842dc82 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5307 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04uart8250: Move under drivers/uartKyösti Mälkki
Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5236 Tested-by: build bot (Jenkins)
2014-03-04uart8250mem: Unify calls with generic UARTKyösti Mälkki
NOTE: UART base for SMM continues to be broken, as it does not use the address resource allocator has assigned. Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5235 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04uart8250io: Unify calls with generic UARTKyösti Mälkki
Change-Id: I6d56648e56f2177e1d5332497321e718df18300c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5234 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04console: Fix includesKyösti Mälkki
Do not pull in console hw-specific prototypes everywhere with console.h as those are not needed for higher levels. Move prototypes for UARTs next to other consoles. Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5232 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04uart8250: Fix and unify baudrate divisor calculationKyösti Mälkki
Divisor is a function of requested baudrate, platform-specific reference clock and amount of oversampling done on the UART reference. Calculate this parameter with divisor rounded to nearest integer. When building without option_table or when there is no entry for baud_rate, CONFIG_TTYS0_BAUD is used for default baudrate. For OxPCIe use of 4 MHz for reference was arbitrary giving correct divisor for 115200 but somewhat inaccurate for lower baudrates. Actual hardware is 62500000 with 16 times oversampling. FIXME: Field for baudrate in lb_tables is still incorrect. Change-Id: I68539738469af780fadd3392263dd9b3d5964d2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5229 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04uart: Do not guard entire include file by config optionsKyösti Mälkki
Do not guard the file by CONFIG_CONSOLE_SERIAL8250 or CONFIG_CONSOLE_SERIAL8250MEM or CONFIG_CONSOLE_SERIAL. Don't do indirect includes for <uart8250.h>. The config-specific options are already properly guarded, and there is no need to guard the register and bit definitions. Change-Id: I7528b18cdc62bc5c22486f037e14002838a2176e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4585 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-03lib/selfboot: s_srcaddr is uninitialized.Edward O'Callaghan
s_srcaddr is uninitialized in the BSS section, leading to a garbage valued operand on the LHS of a '<' on line 383. Change-Id: Ie4fec91b09c70fb1d91ad3918ac3f60653fa1d83 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5314 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-03coreboot: remove unused get_lb_mem() functionAaron Durbin
The get_lb_mem() is no longer used. Therefore, remove it. Change-Id: I2d8427c460cfbb2b7a9870dfd54f4a75738cfb88 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5304 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03selfboot: use bootmem infrastructureAaron Durbin
Instead of packing and unpacking entries in lb_mem use the bootmem infrastructure for performing sanity checks during payload loading. Change-Id: Ica2bee7ebb0f6bf9ded31deac8cb700aa387bc7a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5303 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03coreboot: introduce notion of bootmem for memory map at bootAaron Durbin
The write_coreboot_table() in coreboot_table.c was already using struct memrange for managing and building up the entries that eventually go into the lb_memory table. Abstract that concept out to a bootmem memory map. The bootmem concept can then be used as a basis for loading payloads, for example. Change-Id: I7edbbca6bbd0568f658fde39ca93b126cab88367 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5302 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03coreboot: introduce arch_payload_run()Aaron Durbin
The selfboot() function relied on global variables within the selfboot.c compilation unit. Now that the bounce buffer is a part of struct payload use a new architecture-specific arch_payload_run() function for jumping to the payload. selfboot() can then be removed. Change-Id: Icec74942e94599542148561b3311ce5096ac5ea5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5300 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03selfboot: store bounce buffer in struct payloadAaron Durbin
In order to break the dependency on selfboot for jumping to payload the bounce buffer location needs to be communicated. Therefore, add the bounce buffer to struct payload. Change-Id: I9d9396e5c5bfba7a63940227ee0bdce6cba39578 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5299 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03coreboot: use struct payload for selfload()Aaron Durbin
In order to encapsulate more data for self loading use struct payload as the type. That way modifications to what is needed for payload loading does not introduce more global variables. Change-Id: I5b8facd7881e397ca7de1c04cec747fc1dce2d5f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5298 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03coreboot: move common code to payload_run() from selfboot()Aaron Durbin
The selfboot() routine was perfoming most of the common teardown and stack checking infrastructure. Move that code into payload_run() to prepare removal of the selfboot() function. Change-Id: I29f2a5cfcc692f7a0fe2656cb1cda18158c49c6e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5297 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03coreboot: unify infrastructure for loading payloadsAaron Durbin
A payload can be loaded either from a vboot region or from cbfs. Provide a common place for choosing where the payload is loaded from. Additionally, place the logic in the 'loaders' directory similarly to the ramstage loader infrastructure. Change-Id: I6b0034ea5ebd04a3d058151819ac77a126a6bfe2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5296 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-25Kill ALT_CBFS_LOAD_PAYLOADVladimir Serbinenko
Not used anymore. Change-Id: Icf3a4a7f932776981048b805478582ad2b784182 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5132 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-25Remove CACHE_ROM.Vladimir Serbinenko
With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82, speedup by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs depending on system configuration, hence screwing up I/O access and cache coherency in worst cases. CACHE_ROM requires the user to sanity check their boot output because the feature is brittle. The working configuration is dependent on I/O hole size, ram size, and chipset. Because of this the current implementation can leave a system configured in an inconsistent state leading to unexpected results such as poor performance and/or inconsistent cache-coherency Remove this as a buggy feature until we figure out how to do it properly if necessary. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5146 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-21lib/edid: Don't set vbe_valid in decode_edid.Vladimir Serbinenko
Decoding EDID doesn't yet mean that gfx mode is used. Change-Id: Icedd36f26877754f34dd59233cce72271d7f0b19 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5269 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-19printk: support and use %hh prefixPatrick Georgi
clang complains otherwise. Change-Id: I2ac98d7147ecd3d7064f17f8c9d214d44baedf97 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4717 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-02-16x86: provide infrastructure to backup default SMM regionAaron Durbin
Certain CPUs require the default SMM region to be backed up on resume after a suspend. The reason is that in order to relocate the SMM region the default SMM region has to be used. As coreboot is unaware of how that memory is used it needs to be backed up. Therefore provide a common method for doing this. Change-Id: I65fe1317dc0b2203cb29118564fdba995770ffea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5216 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-15coreboot: infrastructure for different ramstage loadersAaron Durbin
There are 2 methods currently available in coreboot to load ramstage from romstage: cbfs and vboot. The vboot path had to be explicitly enabled and code needed to be added to each chipset to support both. Additionally, many of the paths were duplicated between the two. An additional complication is the presence of having a relocatable ramstage which creates another path with duplication. To rectify this situation provide a common API through the use of a callback to load the ramstage. The rest of the existing logic to handle all the various cases is put in a common place. Change-Id: I5268ce70686cc0d121161a775c3a86ea38a4d8ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5087 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-11SMP: Add arch-agnostic boot_cpu()Kyösti Mälkki
We should not have x86 specific includes in lib/. Change-Id: I18fa9c8017d65c166ffd465038d71f35b30d6f3d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5156 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-11Move hexdump32() to lib/hexdump.Kyösti Mälkki
Needs printk and is not a console core function. Change-Id: Id90a363eca133af4469663c1e8b504baa70471e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5155 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-09mtrr: only add prefetchable resources as WRCOMB for VGA devicesAaron Durbin
Be more conservative and only add VGA devices' prefetchable resources as write-combining in the address space. Previously all prefetchable memory was added as a write-combining memory type. Some hardware incorrectly advertises its BAR as prefetchable when it shouldn't be. A new memranges_add_resources_filter() function is added to provide additional filtering on device and resource. Change-Id: I3fc55b90d8c5b694c5aa9e2f34db1b4ef845ce10 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5169 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2014-02-06uart8250: Drop xmodem supportKyösti Mälkki
Unused and hard-coded to use uart8250 on IO. Change-Id: I3f84c50039a450a2ae97a5fd2af89992f8567e6c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5137 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-06ne2k: Move under drivers/netKyösti Mälkki
Change-Id: I978b6009c09c31be4429f57be40ef82f438f7574 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5135 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-06spkmodem: Move under drivers/pc80Kyösti Mälkki
Change-Id: I46eb17ab19cea8759b3e4822019285cbe907e83a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5134 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-06usbdebug: Move under drivers/usbKyösti Mälkki
Also relocate and split header files, there is some interest for EHCI debug support without PCI. Change-Id: Ibe91730eb72dfe0634fb38bdd184043495e2fb08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5129 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06lib/memrange: Skip 0-sized resources.Vladimir Serbinenko
Change-Id: I44194153817b8e6b641e407fc4a9e0fd5bc3f318 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5152 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06memranges: add memranges_update_tag() functionalityAaron Durbin
The memranges_update_tag() function replaces all instances that are tagged with old_tag and update to new_tag. This can be helpful in the MTRR code by adjusting the address space if certain memory types cause the MTRR usage to become too large. Change-Id: Ie5c405204de2fdd9fd1dd5d6190b223925d6d318 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5150 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-05load_payload: Use 32-bit accesses to speed up decompression.Vladimir Serbinenko
Flash prefers 32-bit sequential access. On some platforms ROM is not cached due to i.a. MTRR shortage. Moreover ROM caching is not currently enabled by default. With this patch payload decompression is sped up by theoretical factor of 4. Test on X201, with caching disabled: Before: 90:load payload 4,470,841 (24,505) 99:selfboot jump 6,073,812 (1,602,971) After: 90:load payload 4,530,979 (17,728) 99:selfboot jump 5,103,408 (572,429) Change-Id: Id17e61316dbbf73f4a837bf173f88bf26c01c62b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5144 Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-01-30coreboot: config to cache ramstage outside CBMEMAaron Durbin
Haswell was the original chipset to store the cache in another area besides CBMEM. However, it was specific to the implementation. Instead, provide a generic way to obtain the location of the ramstage cache. This option is selected using the CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM Kconfig option. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted with baytrail support. Also built for falco successfully. Change-Id: I70d0940f7a8f73640c92a75fd22588c2c234241b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172602 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4876 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30cbmem: Export ACPI GNVS cbmem pointer in coreboot tableDuncan Laurie
This will make it possible for payloads to find the ACPI NVS region which is needed to get base addresses for devices that are in ACPI mode. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot rambi with emmc in ACPI mode Change-Id: Ia67b66ee8bd45ab8270444bbb2802080d31d14eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5015 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-28rmodule: consolidate rmodule stage loadingAaron Durbin
There are 3 places rmodule stages are loaded in the existing code: cbfs and 2 in vboot_wrapper. Much of the code is the same except for a few different cbmem entry ids. Instead provide a common implementation in the rmodule library itself. A structure named rmod_stage_load is introduced to manage the inputs and outputs from the new API. BUG=chrome-os-partner:22866 BRANCH=None TEST=Built and booted successfully. Change-Id: I146055005557e04164e95de4aae8a2bde8713131 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174425 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4897 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-28cbmem: add reference code idsAaron Durbin
In order to identify the ram used in cbmem for reference code blobs add common ids to be consumed by downstream users. BUG=chrome-os-partner:22866 BRANCH=None TEST=Built and booted with ref code support. Noted reference code entries in cbmem. Change-Id: Iae3f0c2c1ffdb2eb0e82a52ee459d25db44c1904 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174424 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4896 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-27coreboot_table: don't add CMOS checksum twice.Vladimir Serbinenko
Checksum is already in cmos_layout.bin. No need to add it twice Change-Id: I6d12f35fd8ff12eee9a17365bbfab38845c09574 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4829 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-22CBMEM: Rename cbmem_reinit()Kyösti Mälkki
This function does not really initialize anything, but only checks for the TOC. Change-Id: I9d100d1823a0b630f5d1175e42a6a15f45266de4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4669 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-22CBMEM: Replace cbmem_initialize() with cbmem_recovery()Kyösti Mälkki
The replacement function confirms CBMEM TOC is wiped clean on power cycles and resets. It also introduces compatibility interface to ease up transition to DYNAMIC_CBMEM. Change-Id: Ic5445c5bff4aff22a43821f3064f2df458b9f250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4668 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-01-14lib: Add log2 ceiling functionAlexandru Gagniuc
Change-Id: Ifb41050e729a0ce314e4d4918e46f82bc7e16bed Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4684 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-14lib/hexdump: Take const void * and size_t as argumentsAlexandru Gagniuc
Representing a memory location as an unsigned long is specific to 32-bit architectures. It also doesn't make sense to represent a length assumed to be positive as a signed integer. With this change, it is no longer necessary to cast a pointer to unsigned long when passing it to hexdump. Change-Id: I641777d940ceac6f37c363051f1e9c1b3ec3ed95 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4575 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13lib: Make log2() available in romstage on ARM, not just x86Alexandru Gagniuc
On x86, log2() is defined as an inline function in arch/io.h. This is a remnant of ROMCC, and forced us to not include clog2.c in romstage. As a result, romstage on ARM has no log2(). Use the inline log2 only with ROMCC, but otherwise, use the one in clog2.c. Change-Id: Ifef2aa0a7b5a1db071a66f2eec0be421b8b2a56d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4681 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-12lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_contentVladimir Serbinenko
Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4659 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-01-06CBMEM: Fix allocation for static CBMEMKyösti Mälkki
CBMEM console buffer size is adjustable in menuconfig, but this would not correctly adjust the overall allocation made for CBMEM. HIGH_MEMORY_SIZE is aligned to 64kB and definitions are moved down in the header file as HIGH_MEMORY_SIZE is not used with DYNAMIC_CBMEM. Try to continue boot even if CBMEM cannot be created. This error would only occur during development of new ports anyways and more log output is better. Change-Id: I4ee2df601b12ab6532ffcae8897775ecaa2fc05f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4621 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-01-06CBMEM: Drop cbmem_base_check()Kyösti Mälkki
This function was for logging only, but we have both base and size already logged elsewhere. Change-Id: Ie6ac71fc859b8fd42fcf851c316a5f888f828dc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4620 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-06CBMEM ACPI: Move resume handlerKyösti Mälkki
Handler is ACPI/x86 specific so move details out of cbmem code. With static CBMEM initialisation, ramstage will need to test for S3 wakeup condition so publish also acpi_is_wakeup(). Change-Id: If591535448cdd24a54262b534c1a828fc13da759 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4619 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-23Coding style: punctuation cleanup [1/2].Idwer Vollering
Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4562 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-21Pit: graphicsRonald G. Minnich
This includes the new dp code, which is better, and the fimd code, which is changed and improved. We took the chance to remove un-needed files, and also to remove some foolish u-boot habits, but not all of them. That will take time. With these changes we get graphics. Since the only mainboards we have with 16 bit graphics are 5:6:5, adjust edid.c to just use that format. If at some future time we need 4:4:4, which seems unlikely, we'll need to add a function to adjust the lb_framebuffer. Note that you can't just divine this from the EDID, as the graphics pipe format need not match the actual final format used. The EDID reading works. We've been requested to support hard-coded EDIDs and that will come in the next revision. Currently the hard-coded EDID is ignored for testing. Change-Id: Ib4d06dc3388ab90c834f94808a51133e5b515a4d Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64240 Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4432 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Calculate transcoder flags based on pipe configFurquan Shaikh
Works fine with all three panels with the change of 6 bits per color. Change-Id: Ia47d152e62d1879150d8cf9a6657b62007ef5c0e Reviewed-on: https://gerrit.chromium.org/gerrit/63762 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4402 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Add simple hexdump functionStefan Reinauer
- prints hex and ascii - detects duplicate all zero lines Change-Id: I557fed34f0f50ae256a019cf893004a0d6cbff7c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/62655 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4392 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Added structure members x_mm and y_mm to edid decodingFurquan Shaikh
Change-Id: I9a628cec4da127a3f072d9611259dad99dfa9d29 Reviewed-on: https://gerrit.chromium.org/gerrit/63125 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4382 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21FUI: Fill in link_m and link_n valuesFurquan Shaikh
... based on the EDID detailed timing values for pixel_clock and link_clock. Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n respectively. Other two undocumented registers 0x6f030 and 0x6f034 correspond to data_m and data_n respectively. Calculations are based on the intel_link_compute_m_n from linux kernel. Currently, the value for 0x6f030 does not come up right with our calculations. Hence, set to hard-coded value. Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e Reviewed-on: https://gerrit.chromium.org/gerrit/62915 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4381 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-12EDID: add fields specialized to the needs of framebuffersRonald G. Minnich
Now that we have horizontal display areas that are not multiples of 32 bytes, things are more complex. We add three struct members (x, y resolution and bytes per line) which are to be filled in by the mainboard as it sets the mode. In future, the EDID code may take a stab at initializing these but the values are context-dependent. Change-Id: Ib9102d6bbf8c66931f5adb1029a04b881a982cfe Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/60514 Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4336 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-03Drop obsolete CONSOLE_LOGBUFStefan Reinauer
This was used by Ron 13ys ago and was never used again ever since. Change-Id: I8ae8a570d67fa0b34b17c9e3709845687f73c724 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59320 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4256 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-12-02global: Fix usage of get_option() to make use of CB_CMOS_ codesAlexandru Gagniuc
Do not directly check the return value of get_option, but instead compare the returned value against a CB_CMOS_ error code, or against CB_SUCCESS. Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4266 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-01Fix build with USE_OPTION_TABLEKyösti Mälkki
Parallelized build might try to build SMM before option_table.h is created. Remove related redundant explicit rules. Change-Id: Ida8b5c408af05adcf3210ce7bfc8a1e5959194c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4299 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-11-30CBMEM console: increase temporary buffer size for non-dynamic CBMEMKyösti Mälkki
Make temporary buffer allocation equal with the allocation in CBMEM and let copy_console_buffer() handle possible truncation. When not using dynamic CBMEM the CBMEM area is initialized late in the ramstage and should be able to hold almost as many characters as the CBMEM can hold. We have seen 40000 was not always enough with logging level set to spew, new default size is 0x10000. Change-Id: If4b143fdf807e28b6766b8b99db5216b767948d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4295 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-11-30cbmem console: reduce temporary buffer size for dynamic CBMEMStefan Reinauer
When using dynamic CBMEM the CBMEM area is initialized before entering ram stage, and so we need a way smaller temporary buffer for the CBMEM console during early bits of ram stage. In practice around 256 bytes are needed, but keep the buffer at 1k so we make sure we don't run out. TEST=Boot tested on pit BRANCH=none BUG=none Change-Id: I462810b7bafbcc57f8e5f9b1d1f38cfdf85fa630 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168575 Reviewed-by: Aaron Durbin <adurbin@chromium.org> [km: cherry-pick 7fd1bbc0 from chromium git] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4293 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-11-30CBMEM console: Prevent buffer overrunKyösti Mälkki
Make sure memcpy target and a possible message telling log was truncated stay within the allocated region for CBMEM console. This fixes observed CBMEM corruption on platforms that do not use CBMEM console during romstage. Those platforms will need an additional fix to reset cursor position to zero on s3 resume. Change-Id: I76501ca3afc716545ca76ebca1119995126a43f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4292 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-11-26Clean up POST codes for Boot State machineDuncan Laurie
Now that there is a clearly defined boot state machine we can add some useful post codes to indicate the current point in the state machine by having it log a post code before the execution of each state. This removes the currently defined POST codes that were used by hardwaremain in favor of a new contiguous range that are defined for each boot state. The reason for this is that the existing codes are mostly used to indicate when something is done, which is confusing for actual debug because POST code debugging relies on knowing what is about to happen (to know what may be at fault) rather than what has just finished. One additonal change is added during device init step as this step often does the bulk of the work, and frequently logs POST codes itself. Therefore in order to keep better track of what device is being initialized POST_BS_DEV_INIT is logged before each device is initialized. interrupted boot with reset button and gathered the eventlog. Mosys has been extended to decode the well-known POST codes: 26 | 2013-06-10 10:32:48 | System boot | 120 27 | 2013-06-10 10:32:48 | Last post code in previous boot | 0x75 | Device Initialize 28 | 2013-06-10 10:32:48 | Extra info from previous boot | PCI | 00:16.0 29 | 2013-06-10 10:32:48 | Reset Button 30 | 2013-06-10 10:32:48 | System Reset Change-Id: Ida1e1129d274d28cbe8e49e4a01483e335a03d96 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58106 Reviewed-on: http://review.coreboot.org/4231 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-23lib/coreboot_table: set type and size of framebuffer tag after ↵Vladimir Serbinenko
fill_lb_framebuffer When testing Ron's patch on qemu I found out that fill_lb_framebuffer overwrites size and tag fields. We need either to fix/check all fill_lb_framebuffer implementations or write tag/size after fill_lb_framebuffer. I prefer later as it's more robust. Change-Id: I98f5bac14f65fb4d990cb21426d402b27f2e8a48 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4263 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-18cbfs: 64-bit cleanupsRonald G. Minnich
cbfs used u32 in a number of cases where uintptr_t was correct. This change builds for both 64-bit and 32-bit boards. Change-Id: If42c722a8a9e8d565d3827f65ed6c2cb8e90ba60 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/4037 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-11-18cbfs: remove unused code and prototypeRonald G. Minnich
The code is wrong (it's calling ntohl on an entry point that is actually already le due to an old cbfs bug) and nothing calls it any more anyway. Change-Id: Ief2c33faf99e3d2fc410524a5aae7bde378f088b Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/4090 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-11-08Add new finalize functions for devices and chipsMarc Jones
Many chipset devices require additional configuration after device init. It is not uncommmon for a device early in the devicetree list to need to change a setting after a device later in the tree does PCI init. A final function call has been added to device ops to handle this case. It is called prior to coreboot table setup. Another problem that is often seen is that the chipset or mainboard need to do some final cleanup just before loading the OS. The chip finalize has been added for this case. It is call after all coreboot tables are setup and the payload is ready to be called. Similar functionality could be implemented with the hardwaremain states, but those don't fit well in the device tree function pointer structure and should be used sparingly. Change-Id: Ib37cce104ae41ec225a8502942d85e54d99ea75f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4012 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-22usbdebug: Fix boards without EARLY_CBMEM_INITKyösti Mälkki
The main usbdebug file lib/usbdebug.c was removed from romstage build with commit f8bf5a10 but the chipset-specific parts were not, leading to unresolved symbol errors for AMD platforms. Add a silent Kconfig variable USBDEBUG_IN_ROMSTAGE for convenient use of this feature. Change-Id: I0cd3fccf2612cf08497aa5c3750c89bf43ff69be Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3983 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15Have option of timestamps, CBMEM console and usbdebug for most boardsKyösti Mälkki
As boards without EARLY_CBMEM_INIT do not initialize CBMEM in romstage, and have no CAR migration, these features are available for ramstage only. Change-Id: Ic3f77ccdedd4e71ba693619c02c9b98b328a0882 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3970 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15timestamps: Fix some lost timestamps for romstageKyösti Mälkki
Timestamps from cbfs_and_run, TS_START_COPYRAM and TS_END_COPYRAM, were lost with commit b766b1c7. Reason is variable ts_table was referencing CAR storage after CAR is torn doesn. Add use of car_get_var() / car_set_var() so the references go to migrated storage in CBMEM. Change-Id: I5a942ad7fd59a04e3a5255f4a3636d37dcfc1591 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3967 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-14Revert "CBMEM: Always have early initialisation"Kyösti Mälkki
This reverts commit de1fe7f655c549e8dce5b34218221890fa5ccc34. While things appeared to work, there were actually invalid references to CAR storage after CAR was torn down on boards without EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be restricted to boards that handle CAR migration properly. Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3968 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-13Rename cpu/x86/car.h to arch/early_variables.hStefan Reinauer
and add an ARMv7 version. Change-Id: I14fbff88d7c2b003dde57a19bf0ba9640d322156 Signed-off-by: Stefan Reinauer <reinauer@google.com> [km: rebased fa004acf8 from chromium git] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3939 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-09-21CBMEM: Always select CAR_MIGRATIONKyösti Mälkki
If romstage does not make cbmem_initialize() call, linker should optimize the code for CAR migration away. This simplifies design of CBMEM console by a considerable amount. As console buffer is now migrated within cbmem_initialize() call there is no longer need for cbmemc_reinit() call made at end of romstage. Change-Id: I8675ecaafb641fa02675e9ba3f374caa8e240f1d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3916 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21CBMEM: Always have early initialisationKyösti Mälkki
Assume EARLY_CBMEM_INIT=y everywhere and remove option from Kconfig. If romstage does not make the cbmem_initialize() call, features like COLLECT_TIMESTAMPS and early CBMEM_CONSOLE will execute during romstage, but that data will get lost as no CAR migration is executed. Change-Id: I5615645ed0f5fd78fbc372cf5c3da71a3134dd85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3917 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21ROMCC boards: Fix builds with CBMEM console, timestamps or usbdebugKyösti Mälkki
These features depend on CAR_GLOBAL region, which is not available when romstage is built with ROMCC. Exclude these from romstage, keep them available for ramstage. A follow-up patch will fix the dependencies and allows enabling these features in menuconfig. Change-Id: I9de5ad41ea733655a3fbdc734646f818e39cc471 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3919 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21CBMEM console: Support late initKyösti Mälkki
It is not compulsory to have CBMEM console initialised in romstage, so try add the CBMEM table entry again in ramstage, if not found. Change-Id: I96ab502df7f05d6bf1d6e6fa84d395ef6306b525 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3915 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21timestamps: Only collect from BSP CPUKyösti Mälkki
We only have one table to collect timestamps into. Change-Id: I80180fe9a05226f0351c3e66eacaf2d0cb82c924 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3912 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21timestamps: Stash early timestamps in CAR_GLOBALKyösti Mälkki
Change-Id: I87b454c748cf885491d5b38bfe53a2ec0e9f38c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3910 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21timestamps: Use stash before CBMEM is usableKyösti Mälkki
Change-Id: I9e927abdb1d7d9c233de5620a9a65b419e803ebf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-20usbdebug: Allow an USB hub on the debug dongleKyösti Mälkki
Some development kits with USB 2.0 HS OTG have an USB hub instead of being directly connected to the USB host/device controller. Send the necessary initialisation sequence, using HUB CLASS requests of PORT_POWER and PORT_RESET to enable a pre-selected port number where a device supporting debug descriptor is located. This also adds the Kconfig option for BeagleBone. Change-Id: I7a5d0ba0962a9ca06bf3196232ed4a03bdfb2b06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3925 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-09-17Fix whitespace leaked into treeKyösti Mälkki
Clean whitespace errors that have gotten past lint-stable-003-whitespace and gerrit review. Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3920 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-11CBMEM: Rename high_tables variables and make them staticKyösti Mälkki
Old name was too much x86. All external references have been removed. Change-Id: I982b9abfcee57a7ea421c245dadb84342949efae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3906 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM: Drop parameters from cbmem_init()Kyösti Mälkki
The parameters can be dropped as initialisation always happens for the region resolved with cbmem_locate_table(). This is no longer referenced externally, make it static. Change-Id: Ia40350a5232dcbf30aca7b5998e7995114c44551 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM: Drop parameter from cbmem_reinit()Kyösti Mälkki
Function is always called with get_top_of_ram() - HIGH_MEMORY_SIZE which equals cbmem_base, thus no need to pass it as a parameter. Change-Id: If026cb567ff534716cd9200cdffa08b21ac0c162 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3564 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM x86: Unify get_cbmem_toc()Kyösti Mälkki
Remove any chipset-specific implementations and use arch-specific implementation of get_cbmem_table() instead. Change-Id: I338ee2c1bd51f5e517462115170dc926e040159e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3907 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM: Backup top_of_ram instead of cbmem_tocKyösti Mälkki
AMD northbridges have a complex way to resolve top_of_ram. Once it is resolved, it is stored in NVRAM to be used on resume. TODO: Redesign these get_top_of_ram() functions from scratch. Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM: Add cbmem_locate_table()Kyösti Mälkki
For both romstage and ramstage, this calls an arch-specific function get_cbmem_table() to resolve the base and size of CBMEM region. In ramstage, the result is cached as the query may be relatively slow involving multiple PCI configuration reads. For x86 CBMEM tables are located right below top of low ram and have fixed size of HIGH_MEMORY_SIZE in EARLY_CBMEM_INIT implementation. Change-Id: Ie8d16eb30cd5c3860fff243f36bd4e7d8827a782 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3558 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM: Unify get_top_of_ram()Kyösti Mälkki
Change-Id: Ic40a51638873642f33c74d80ac41cf082b2fb177 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3904 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM tables: Remove references to global high_tables_baseKyösti Mälkki
Unify checks and writing of CBMEM tables for x86 and ARMv7. Change-Id: I89c012bce1b86d0710748719a8840ec532ce6939 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3559 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM: Add cbmem_late_set_table() and drop references to high_tables_baseKyösti Mälkki
This helper function is for compatibility only for chipsets that do not implement get_top_of_ram() to support early CBMEM. Also remove references to globals high_tables_base and _size under arch/ and from two ARMv7 boards. Change-Id: I17eee30635a0368b2ada06e0698425c5ef0ecc53 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3902 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-06usbdebug: Use CAR migrationKyösti Mälkki
If we already initialized EHCI controller and USB device in romstage, locate active configuration from salvaged CAR_GLOBAL and avoid doing the hardware initialisation again. Change-Id: I7cb3a359488b25abc9de49c96c0197f6563a4a2c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3476 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-06usbdebug: Dump low-level protocol detailsKyösti Mälkki
Dumping these EHCI host controller registers is useful to solve problems with debug devices. Change-Id: I0610cecca57b1b952d4f87211dd00c8c0bc398b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3866 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-06usbdebug: Adjust endpoint retry timeoutsKyösti Mälkki
Change Setup Stage of control messages to have no retries, while data and status stages may retry until timing out after 1000 retries. The correct amount of retries might vary by endpoint and device dongle used, so make it a variable. Change-Id: I63313f994d0bd3444a3aab527ca942da5de9e6fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3882 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-06usbdebug: Adjust transaction retriesKyösti Mälkki
Transaction consistently completes with 80 to 150 status reads on my setups. Hardware should always be able to complete this within 125us as the debug port is serviced at the beginning of each microframe. Timeout is set to DBGP_MICROFRAME_TIMEOUT_LOOPS=1000 status reads. Do not retry transactions if this timeout is reached as the host controller probably needs full re-initialisation to recover. If this timeout is not reached, but a transaction is corrupted on the wire, or it is otherwise not properly delivered to the USB device, transaction is retried upto DBGP_MICROFRAME_RETRIES=10 times. Change-Id: I44bc0a1bd194cdb5a2c13d5b81fc39bc568ae054 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3881 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-31Remove NRV2B compression supportPatrick Georgi
It wasn't even hooked up to the build system anymore. Change-Id: I4b962ffd945b39451e19da3ec2f7b8e0eecf2e53 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/3892 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-08-29usbdebug: Fix control messagesKyösti Mälkki
Add support for control messages with a write of data stage. Add status stage after a read of non-zero length data stage. Do not retry control message if device responds with STALL. Change-Id: I16fb9ae39630b975af5461b63d050b9adaccef0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3867 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29usbdebug: Use separate data toggle for each pipeKyösti Mälkki
USB defines a mechanism to detect certain cases of lost handshakes using an alternating data sequence number, referred to as data toggling. This patch fixes each pipe to have its own tracking of the data toggle state. Change-Id: I62420bdaeadd0842da3189428a37eeb10c646900 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3865 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 14:33:42 +0000