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2018-08-08lib/bootmem.c: Remove unused setting of variable "begin"Richard Spiegel
The variable "begin" is extracted from the structure, but 4 lines below it's overwritten with "end - size". This causes a static build scan error that should be fixed. Remove the initial assignment of variable "begin". BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I0a265747e61289f045c5cac09e40478bd31e16fc Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27886 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-03gpio: Change gpio_baseX_value() function return types to unsignedJulius Werner
This patch changes the return type of gpio_base2_value() and related functions from int to uint32_t. This makes more sense now that board_id() and related functions (which are the primary use case) also return that type. It's unlikely that we'll ever read a strapping of 32 GPIOs in a row, but if we did, we'd probably want to treat it as unsigned. Change-Id: I8fb7e3a7c76cb886aed40d0ada1f545180e43117 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-28util/cbmem: Add cbmem TCPA log supportPhilipp Deppenwiese
* Read and print the TCPA ACPI log. Change-Id: Ie2253d86cfc675d45b0a728794cc784215401f4a Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/26244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-20write_tables: return a pointer to the tableRonald G. Minnich
The write_tables function was void. It is a bit more useful for loading payloads from the romstage if it returns a pointer to the table it creates. Change-Id: I6eeaf3e16bcbaf1e7ec3eada8026c466d2fb6f5a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/27537 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-12Coverity: Fix CID1393979Patrick Rudolph
Fix resource leak in dt_set_bin_prop_by_path(). Change-Id: I1c4d7e01b25847a2091ad90d2d70711beae55905 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-09src/{ec,include,lib}: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I447aaa1850b7e8b514a8c4c04bf5b426d3d1cd0a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-02src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I3873cc8ff82cb043e4867a6fe8c1f253ab18714a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-28devicetree: Add method to delete property by namePatrick Rudolph
Will be used on Cavium SoC to delete devicetree entries that aren't available with the board/configuration. Change-Id: I7c58a2411206bca62d0e96fa627530e937383ac9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-28vboot: Fix linking error with USE_OPTION_TABLE enabledPatrick Rudolph
Fix a linking problem with VBOOT and USE_OPTION_TABLE enabled. Make use of cbfs_locate_file_in_region() and always search the cmos_layout.bin in the 'COREBOOT' region. With this change applied there's no need to include the vboot_locator in SMM any more, we can't break NVRAM with different CMOS layouts, and we keep VBOOT and non VBOOT behaviour the same. Only include cmos_layout.bin and cmos.default in RO region. Add notes explaining the decisions. Tested on Intel Sandybridge, builds and boots with vboot enabled. Change-Id: I10ae94d7936581bbb5ea49384122062bd4934ea5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-27lib/rmodule: Fix indentationKyösti Mälkki
Change-Id: Ieb809a078356f696afd813c39c65da1d7c7482c8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-27stage_cache: Disable when APCI S3 is not possibleKyösti Mälkki
Don't consume CBMEM for stage cache when we would never use it. Change-Id: I606e0457ff3085822554c4041fc56f0d28cc9c2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-19lib: Add FIT payload supportPatrick Rudolph
* Add support for parsing and booting FIT payloads. * Build fit loader code from depthcharge. * Fix coding style. * Add Kconfig option to add compiletime support for FIT. * Add support for initrd. * Add default compat strings * Apply optional devicetree fixups using dt_apply_fixups Starting at this point the CBFS payload/ can be either SELF or FIT. Tested on Cavium SoC: Parses and loads a Linux kernel 4.16.3. Tested on Cavium SoC: Parses and loads a Linux kernel 4.15.0. Tested on Cavium SoC: Parses and loads a Linux kernel 4.1.52. Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-19lib: Raw import FIT parserPatrick Rudolph
Import from https://chromium.googlesource.com/chromiumos/platform/depthcharge Coding style and coreboot integration will be done in a separate commit. Change-Id: Iee56db328d7eeffb0eaf829841243b0b9195c199 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-19lib/prog_loaders: Move argument selection into selfloadPatrick Rudolph
Set the payload argument in selfload, as other (non self) payloads, are going to set a different argument. Change-Id: I994f604fc4501e0e3b00165819f796b1b8275d8c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25861 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14src: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14lib/device_tree: Add method to get phandlePatrick Rudolph
Add a method to retrieve a node's phandle. Useful for board specific devicetree manipulations. Change-Id: I966151ad7e82fc678ab4f56cf9b5868ef39398e0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-12arch/x86: Fix payload loading via bounce-bufferKyösti Mälkki
Fix regression (supposedly) after commit: 23d62dd lib/bootmem: Add more bootmem tags Without RELOCATABLE_RAMSTAGE, payload is allowed to overwrite memory regions of the running ramstage. This case is handled gracefully via a bounce-buffer implementation in arch/x86/boot.c. Change-Id: I1c9bbdb963a7210d0817a7a990a70a1e4fc03624 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-12bootmem: Clarify usage with bounce-bufferKyösti Mälkki
Add bootmem_targets_usable_with_bounce() to handle cases of payload loading via bounce-buffer. Change-Id: I9ebbc621f8810c0317d7c97c6b4cdd41527ddcbb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26985 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11{src,util}: Use NULL instead of 0 for pointerElyes HAOUAS
Change-Id: I75fa4577055f25dde0a8b1044c005bba72cabd92 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-11selfboot: Move x86 quirk under archKyösti Mälkki
Making exceptions for some payload to be loaded near and under 1 MiB boundary sounds like a legacy 16-bit x86 BIOS thing we generally do not want under lib/. Change-Id: I8e8336a03d6f06d8f022c880a8334fe19a777f0a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-04src/lib: Remove unneeded 'console.h' includeElyes HAOUAS
Change-Id: Ibdda3dc52f5b61077f91f4cffb4f86b2955aab74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04lib/cbfs: Optimise LZMA away from romstageKyösti Mälkki
If we have POSTCAR_STAGE there is no need for romstage to include LZMA decompression code. Reduces romstage by about 4 kiB on x86. Change-Id: I4c475986b2a94e5cd540c3eead433ed6c0a815ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-04lib/coreboot_table.c: Remove unneeded includeElyes HAOUAS
Change-Id: I6e0d9e10d4f2ea224a19ef11481148f21d29857f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26795 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31Remove AMD K8 cpu and northbridge supportKyösti Mälkki
Change-Id: I9c53dfa93bf906334f5c80e4525a1c27153656a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-22Introduce bootblock self-decompressionJulius Werner
Masked ROMs are the silent killers of boot speed on devices without memory-mapped SPI flash. They often contain awfully slow SPI drivers (presumably bit-banged) that take hundreds of milliseconds to load our bootblock, and every extra kilobyte of bootblock size has a hugely disproportionate impact on boot speed. The coreboot timestamps can never show that component, but it impacts our users all the same. This patch tries to alleviate that issue a bit by allowing us to compress the bootblock with LZ4, which can cut its size down to nearly half. Of course, masked ROMs usually don't come with decompression algorithms built in, so we need to introduce a little decompression stub that can decompress the rest of the bootblock. This is done by creating a new "decompressor" stage which runs before the bootblock, but includes the compressed bootblock code in its data section. It needs to be as small as possible to get a real benefit from this approach, which means no device drivers, no console output, no exception handling, etc. Besides the decompression algorithm itself we only include the timer driver so that we can measure the boot speed impact of decompression. On ARM and ARM64 systems, we also need to give SoC code a chance to initialize the MMU, since running decompression without MMU is prohibitively slow on these architectures. This feature is implemented for ARM and ARM64 architectures for now, although most of it is architecture-independent and it should be relatively simple to port to other platforms where a masked ROM loads the bootblock into SRAM. It is also supposed to be a clean starting point from which later optimizations can hopefully cut down the decompression stub size (currently ~4K on RK3399) a bit more. NOTE: Bootblock compression is not for everyone. Possible side effects include trying to run LZ4 on CPUs that come out of reset extremely underclocked or enabling this too early in SoC bring-up and getting frustrated trying to find issues in an undebuggable environment. Ask your SoC vendor if bootblock compression is right for you. Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-22bootblock: Allow more timestamps in bootblock_main_with_timestamp()Julius Werner
This patch adds more parameters to bootblock_main_with_timestamp() to give callers the opportunity to add additional timestamps that were recorded in the platform-specific initialization phase. Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-19lib/gnat: Drop Restriction `No_Exception_Propagation`Nico Huber
It turns out that even with the `-gnatp` switch to suppress runtime checks, the compiler is still allowed to generate them (it only doesn't have to). If we can't control generation of checks, we also can't make assumptions about propagation of their exceptions. The compiler warning that led to this change seems spurious, though (the check might be generated, but is dropped later). So we might revert this decision if the compiler can be fixed. Change-Id: I7470d74b1f96f90d0d15b24dfd636d5f1c778d46 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-16lib/prog_loaders: Store CBFS type in struct progPatrick Rudolph
Store the type of the loaded program after locating the file and add a method to retrieve the type. Will be used to distinguish between SELF and FIT payloads. Change-Id: Ic226e7e028d722ab9e3c6f7f1c22bde2a1cd8a85 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26028 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14timestamp: Increase max number of timestampsRaul E Rangel
I'm increasing the max because when AGESA tracing is enabled it will use over 120 entries. I added some padding to the number incase more probes are added. This only affects ramstage so the extra ram shouldn't matter. BUG=b:64549506 TEST=boot on grunt and ran cbmem -t Change-Id: I7a3d2d09c91c9e302d139e7f65fa9c85c4594de4 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-10bootmem: Keep OS memory map separate from the startJulius Werner
The patch series ending in 64049be (lib/bootmem: Add method to walk OS POV memory tables) expanded the bootmem framework to also keep track of memory regions that are only relevant while coreboot is still executing, such as the ramstage code and data. Mixing this into the exsting bootmem ranges has already caused an issue on CONFIG_RELOCATEABLE_RAMSTAGE boards, because the ramstage code in CBMEM is marked as BM_RAMSTAGE which ends up getting translated back to LB_RAM in the OS tables. This was fixed in 1ecec5f (lib/bootmem: ensure ramstage memory isn't given to OS) for this specific case, but unfortunately Arm boards can have a similar problem where their stack space is sometimes located in an SRAM region that should not be made available as RAM to the OS. Since both the resources made available to the OS and the regions reserved for coreboot can be different for each platform, we should find a generic solution to this rather than trying to deal with each issue individually. This patch solves the problem by keeping the OS point of view and the coreboot-specific ranges separate from the start, rather than cloning it out later. Ranges only relevant to the coreboot view will never touch the OS-specific layout, to avoid the problem of losing information about the original memory type of the underlying region that needs to be restored for the OS view. This both supersedes the RELOCATABLE_RAMSTAGE fix and resolves the problems on Arm boards. Change-Id: I7bb018456b58ad9b0cfb0b8da8c26b791b487fbb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26182 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09{device,drivers,lib,mb,nb}: Use only one space after 'if'Elyes HAOUAS
Change-Id: I390191fb58605d1bd6a2e5d19a9dfa7c8493e6b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09lib/nhlt: add support for passing subsystem_id to endpoint's structureHarsha Priya
This patch adds subsystem_id to nhlt structure whose value is passed on to the endpoint's structure. Its default value is retained to be NHLT_SSID. Change-Id: Iad53f27e958f50e02e928cd8fa60d8397ca0eb06 Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/26046 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-07lib/bootmem: ensure ramstage memory isn't given to OSAaron Durbin
When RELOCATABLE_RAMSTAGE is employed ramstage lives within the cbmem area. Don't mark it as OS usable under that circumstance. Change-Id: Ie15775806632bd943b8217c433bc13708904c696 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/26117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-04lib/bootmem: Add method to walk OS POV memory tablesPatrick Rudolph
Add method to walk memory tables from OS point of view. The tables don't change when modifiying bootmem entries and doesn't contain bootmem specific tags. Change-Id: Iee332a9821d12a7d9a684063b77b0502febd8d7d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04lib/bootmem: Add method to walk memory tablesPatrick Rudolph
Add a method to walk bootmem memory tables and call a function for each memory range. The tables might not match with OS sight of view. Return true if the callback function returned false. Required for FIT support in coreboot to find a usable RAM region. Tested on Cavium SoC. Change-Id: I0004e5ad5fe2289827f370f0d0f9979d3cbd3926 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04lib/bootmem: Add more bootmem tagsPatrick Rudolph
Introduce new bootmem tags to allow more fine grained control over buffer allocation on various platforms. The new tags are: BM_MEM_RAMSTAGE : Memory where any kind of boot firmware resides and that should not be touched by bootmem (by example: stack, TTB, program, ...). BM_MEM_PAYLOAD : Memory where any kind of payload resides and that should not be touched by bootmem. Starting with this commit all bootmem methods will no longer see memory that is used by coreboot as usable RAM. Bootmem changes: * Introduce a weak function to add platform specific memranges. * Mark memory allocated by bootmem as BM_TAG_PAYLOAD. * Assert on failures. * Add _stack and _program as BM_MEM_RAMSTAGE. ARMv7 and ARMv8 specific changes: * Add _ttb and _postram_cbfs_cache as BM_MEM_RAMSTAGE. ARMv7 specific changes: * Add _ttb_subtables as BM_MEM_RAMSTAGE. Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02lib/cbfs.c: fix typoPatrick Georgi
Change-Id: I39c12ab3f28b5448fa4f46958cf23f2623a92378 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/25928 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-30lib/bootmem: Introduce custom bootmem tagsPatrick Rudolph
Introduce bootmem custom memory tags and use them instead of reusing LB_MEM tags. Use asserts in bootmem_add_range to verify parameters. Tested with uImage payload on Cavium SoC. Change-Id: I7be8fa792fc7933ca218ecd43d250d3a9c55caa6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-30lib/devicetree: Integrate flattened devicetree supportPatrick Rudolph
* Adapt to coreboot coding style. * Use coreboot's endian conversion functions. * Fix header and header guards. * Get rid of unused functions. * Add Kconfig to build it on ramstage. * Replace size32 with ALIGN_UP and DIV_ROUND_UP. * Add NULL pointer checks * Convert constants to defines Required for Cavium's BDK and uImage FIT support. Change-Id: I6e6cd9f78fb402bd54d684097326d26eb78d552a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-30lib: Raw import FDT devicetree from depthchargePatrick Rudolph
Import from https://chromium.googlesource.com/chromiumos/platform/depthcharge Required for general devicetree patching and FIT support. Coding style and coreboot integration will be done in a separate commit. Change-Id: Ida75d4786eae38d84bfc71bf53573dafca8eda40 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-24lib/ext_stage_cache: include prog arg in stage cache metadataAaron Durbin
In commit d87e4b34 (stage_cache: Add rmodule params in metadata) the cbmem stage cache was updatd to keep track of the arg from struct prog in the metadata. However, external stage cache did not get the same change. Fix that. BUG=b:72728953 Change-Id: Ifdaaa255cac0f413856410ff61bfb411a9554a31 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-17cbfs: Add cbfs_boot_load_file()T Michael Turney
Generalize cbfs_boot_load_struct() by passing in CBFS type Change-Id: I6e5f845cb4ce5b00f01a39619919f85e39028f19 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-16lib/bootmem: tightly couple bootmem_init to bootmem_write_memory_tableAaron Durbin
In https://review.coreboot.org/25383 people were confused about the ordering of bootmem calls w.r.t. when entries are exposed to the OS. To alleviate this add a notion of bootmem being initialized. In addition to that, only mark bootmem initialized when bootmem_write_memory_table() is called. Any other calls to bootmem before that will report an error on the console. Change-Id: I5bc31f555038ccabb82d902c54f95858679b1695 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-11lib/memrange: Introduce method to clone memrangePatrick Rudolph
Add a new method to clone an existing memrange with all of its entries. Required for new bootmem type LB_MEM_RAM_DONT_OVERLAP. Change-Id: I64b27bf2611ca310385ef680f030a3e4aa0c2680 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25582 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11src/lib/dimm_info_util.c: Add methods to convert from SMBIOS to SPDRaul E Rangel
AMD AGESA returns DIMM info in SMBIOS format. dimm_info expects the data in SPD format. These methods will be used to update amd_late_init.c so it sets the correct values. BUG=b:65403853 TEST=Built and booted grunt. Methods are not called in this commit. So they were tested with the later commit by verifying the output of dmidecode. Change-Id: Id9fa98e9aad83dfd0a86f45e18b3c312665dce9b Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/25412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-09lib/lzmadecode: Add block around `UpdateBit1()`Paul Menzel
Fix the error below. ``` src/lib/lzmadecode.c: In function 'LzmaDecode': src/lib/lzmadecode.c:77:2: error: macro expands to multiple statements \ [-Werror=multistatement-macros] Range -= bound; \ ^~~~~ src/lib/lzmadecode.c:300:7: note: in expansion of macro 'UpdateBit1' UpdateBit1(prob); ^~~~~~~~~~ src/lib/lzmadecode.c:299:8: note: some parts of macro expansion are not \ guarded by this 'else' clause } else ^~~~ cc1: all warnings being treated as errors ``` The macro is defined as below. #define UpdateBit1(p) \ Range -= bound; \ Code -= bound; \ *(p) -= (*(p)) >> kNumMoveBits Found-by: gcc-8 (Debian 8-20180402-1) 8.0.1 20180402 (experimental) [trunk revision 259004] Fixes: 35af5c47 (src/lib: Fix spacing) Change-Id: Ife0688541e23c05e26e429a6d8caee7e2d425b1b Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/25549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-03-26lib/lzma: Respect dstn argumentPatrick Rudolph
Don't write more bytes than the caller requests. Based on I484b5c1e3809781033d146609a35a9e5e666c8ed. Change-Id: I336de417c7cd6f35cf84947fc4ae161c15bd93ef Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-03-09Timestamps: Add option to print timestamps to debug consoleMartin Roth
Prints the timestamp name and value to the debug console if enabled in Kconfig. Change-Id: Ie6e6a4877fefec45fb987ceae7d42de6ce768159 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-03-08coreboot_table: Print GPIO state correctly for lb_gpiosJulius Werner
Looks like there's a typo in the GPIO state table we print as part of assembling the coreboot tables. Of course, high GPIOs are represented as 1 and low GPIOs as 0. Fix this display bug. Change-Id: I59b4d49955c13f920576dd09f463e2d399ab64e0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25022 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-05lib: Add delay.c to smmFurquan Shaikh
BUG=b:74083107 Change-Id: I98ab5c84268e8754fbaf6a30cd26fe1084e45a20 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-07lib/stage_cache: Add save/get raw storageMarshall Dawson
Leverage the stage_cache mechanism to store a non-specific type of data. This is not interesting when the location for the cache is in cbmem. However it will be more useful when an external location is used, e.g. when the cache is in TSEG, locked from user modification. Change-Id: Iaf0b25ebe14c176bbd24fc8942f902f627ca8e6f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-01lib/stage_cache: Add debug messages for failuresMarshall Dawson
Communicate additional status to the console when the save and load functions do not function as expected. The most likely scenario for an error is when using a cache that is external to cbmem, and restricted in size. Change-Id: Ic9a709c11152b3b9cb40abfc204151f9636b5a4c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-25lib: include timer.c for all stages for GENERIC_UDELAYAaron Durbin
In order to fully utilize GENERIC_UDELAY in smm and postcar the udelay() implementation needs to be included. Do that. BUG=b:72378235,b:72170796 Change-Id: Ia20c1ed41ee439bb079e00fb7bd9c1855e31e349 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07boardid: Add helpers to read sku_id strapping into coreboot tablesJulius Werner
On many recent Chrome OS boards, the desire to unite more configurations under the same image has led to the need of a "SKU ID" that identifies different configurations of the same board (e.g. with certain optional components stuffed or not stuffed, or replaced with a comparable component). This is markedly different from the existing "board ID", because that is reserved to count "revisions" -- changes made to the same configuration over time during the development process. This patch adds support to have a mainboard define this SKU ID and pass it through the coreboot table like we already have for board IDs. Change-Id: I8aabffe8e1003b0d6fb70d689ae513ca4b46aeda Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22696 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Switch from Kconfig to weak functionsJulius Werner
This patch switches the board_id and ram_code helper framework to use weak functions rather than Kconfigs to determine whether the board supplies these IDs. This cuts down on the amount of boilerplate Kconfigs many boards have to set and also gives them more flexibility, such as being able to determine at runtime whether a given ID is present. Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22695 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Minor clean up and standardizationJulius Werner
Merge the different coreboot table strapping ID structures into one because they're really just all the same, and I want to add more. Make the signature of the board_id() function return a uint32_t because that's also what goes in the coreboot table. Add a printk to the generic code handling strapping IDs in ramstage so that not every individual mainboard implementation needs its own print. (In turn, remove one such print from fsp1_1 code because it's in the way of my next patch.) Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06Kconfig: Remove BOARD_ID_MANUAL optionJulius Werner
The BOARD_ID_MANUAL and BOARD_ID_STRING options were introduced for the Urara board which is now long dead, and have never been used anywhere else. They were trying to do something that we usually handle with a separate SKU ID these days, whereas BOARD_ID is supposed to be reserved for different revisions of the same board/SKU. Get rid of it to make further refactoring of other options easier. Also shove some stuff back into the Urara mainboard that should've never crept into generic headers. Change-Id: I4e7018066eadb38bced96d8eca2ffd4f0dd17110 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-07src: Fix all Siemens copyrightsMario Scheithauer
Some Siemens copyright entries incorrectly contain a dot at the end of the line. This is fixed with this patch. Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-07lib/ramtest: Add commentPatrick Rudolph
Add a comment about the tested RAM region size. Change-Id: I29e99a06777bd21a65aa67049ceede4fd8adb603 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Maximilian Schander <coreboot@mimoja.de> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-11-03lib/reg_script.c: Remove unused assignmentPaul Menzel
Fix the warning below. ``` CC bootblock/lib/reg_script.o src/lib/reg_script.c:375:11: warning: Value stored to 'value' during its \ initialization is never read uint64_t value = msr.hi; ^~~~~ ~~~~~~ ``` Found-by: Clang static analyzer scan-build (clang version 4.0.1-6 (tags/RELEASE_401/final)) Fixes: fd461e39 (regscript: Add support for MSR type) Change-Id: I218e45d12f2f00e2ad4cfe5410029f407b57568d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-31intel/common/smbus: increase spd read performanceKane Chen
This change increases the spd read performance by using smbus word access. BUG=b:67021853 TEST=boot to os and find 80~100 ms boot time improvement on one dimm Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/22072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-28lib: Prepare for libhwbase' generated config fileNico Huber
Add new libhwbase options and add a class for files generated during build. This follows the same pattern as for libgfxinit. Change-Id: Ie5b84992fa687e4e94b6d959a64086c638f66eb8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-20lib/gpio: constify array inputsAaron Durbin
The arrays of gpio_t are not manipulated in any way within the gpio library. Add const to indicate that. Change-Id: Ie32ab9de967ece22317e2b97b62e85b0757b910d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-16drivers/elog: Fix debug build errorsJohn E. Kabat Jr
Add hexdump.c to Makefile.inc and change an elog_debug format to use %z for size_t arguments. This corrects build errors when ELOG_DEBUG is used. Change-Id: I3d5547eed8ada7c4bdcbbb8bb9d6965ade73beda Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com> Reviewed-on: https://review.coreboot.org/21769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-28Kconfig: Move libhwbase related options into lib/KconfigNico Huber
More will follow so better move them where they are used. Also remove defaults and add dependencies to not clutter .config files up that don't have any of these options selected. Change-Id: I3a255c821cc26aeb66e4fd6adf7142d7e856f5ac Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-26Use stopwatch_wait_until_expired where applicableJonathan Neuschäfer
Change-Id: I4d6c6810b91294a7e401a4a1a446218c04c98e55 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-09-26src/lib/Makefile.inc: Remove loaders subdirectoryJonathan Neuschäfer
src/lib/loaders was removed in commit 899d13d0df ("cbfs: new API and better program loading"). Change-Id: Ic7a9f5d83c5f9445bf24970e0c8cc645dd1944ff Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-23toolchain: Always use GCC for Ada sourcesNico Huber
We can't use $(CC) in case it's set to Clang. TEST=Built one target with Ada sources before and after this change and verified that the same compiler commands are emitted. Change-Id: I9b8ea35352d74b364f09fc12d8d981ca42f8b7c8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-23toolchain: Use xcompile proposed CFLAGS for AdaNico Huber
We don't output special ADAFLAGS in xcompile but its CFLAGS are compatible with and necessary for Ada too. So use the latter and make sure we use them for libgnat too. Fixes i386 builds with x86_64 toolchain. TEST=Gave libgfxinit a shot on lenovo/t420. Change-Id: I0d13f182acfaa9bd1b608edd8a508c4ceedef3b3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-21src/lib/ubsan: Indent macros to improve readabilityJonathan Neuschäfer
Change-Id: Ide4e58e584a1a2bbc1b861e2c4dd943a1aeb35ab Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-14timestamp: Add function to get time since bootWerner Zeh
Add a function to retrieve the elapsed time since boot. For that purpose use the base time in the timestamp table among with the current timestamp at call time of the function. So more precise the returned time is the elapsed time since the timestamp was initialized scaled in microseconds. This was chosen to get a reliable value even on platforms where the TSC might not be reset on software reset or warm start. Change-Id: Ib93ad89078645c0ebe256048cb48f9622c90451f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/21516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08stage_cache: Add rmodule params in metadataKyösti Mälkki
The change allows to update rmodule parameters after it has been loaded from stage cache. Change-Id: Ib825ffe245d447ad3a8246f7dbd52c6e34103a0c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-06postcar: Add cbmem_stage_cacheKyösti Mälkki
S3 resume path executing through postcar was unable to utilise cached ramstage in CBMEM. Change-Id: Icc8947c701ca32b4f261ebb78dfc1215b7ed2da0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-04lib/cbmem: provide optional cbmem top initialization hookAaron Durbin
Provide a hook to allow an optional one-time cbmem_top() initialization. The new function, cbmem_top_init(), is called on the first expected initialization of cbmem based on the Kconfig options LATE_CBMEM_INIT and EARLY_CBMEM_INIT. Change-Id: I89edd2d11f226217c8e2aaca829b4f375a2cff28 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03lib/cbmem: use globals for non CAR global migration platformsAaron Durbin
For CAR platforms which don't migrate globals real globals can be directly used. This alleviates the need to peform partial recovery on every cbmem access which in turn acts like all non-CAR platforms or any stages which execute entirely out of RAM. Change-Id: I31c08dd6473324424d5d42fe6b56d42fe635929e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03lib/cbmem: remove cbmem_region_used()Aaron Durbin
The cbmem_region_used() function wasn't being utilized outside this module. Threfore, reduce the surface area. Change-Id: I28a9d02221048ab0aa4cd3d986d17ee7692ce636 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03lib/imd_cbmem: remove unused #includeAaron Durbin
Change-Id: I18a08faa5f9f5330cdb509c27a8ab7a3aa8e5b73 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03lib/imd_cbmem: remove unused funcitonAaron Durbin
The cbmem_fail_recovery() function was no longer used. I'm not sure why the compiler never complained. Regardless, delete it. Change-Id: I7d94118068064c61252d1b5ca9d8e92658a699e0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-30lib/program.ld: Guard .id section placementNico Huber
For x86, we place the .id section at 4GiB - CONFIG_ID_SECTION_OFFSET. To take effect, we have to guard the conflicting default placement in `program.ld`. Also, as we only include the .id section into the boot- block, guard it by ENV_BOOTBLOCK too. Change-Id: Idc7cbd670ce4f75b7790ff8d95578683e355ba7e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20810 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-07-27timestamp: Apply factor to recorded stampsKyösti Mälkki
If we dont have a constant TSC rate, timestamp table has odd leaps and may appear to run backwards. Add functionality to apply a factor such that all stamps are in the same timebase. Change-Id: Idab9c2c00e117c4d247db8cc9a2897640fa01edd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-26Port cmos.default handling to C environment bootblockNico Huber
Gather related code in the new file drivers/pc80/rtc/mc146818rtc_boot.c, call sanitize_cmos() from C environment bootblock. Change-Id: Ia5c64de208a5986299c0508d0e11eeb8473deef1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25src/lib: Fix checkpatch warning: no spaces at the start of a lineMartin Roth
Change-Id: I332c44c6db0a5ea05db076474caf77d6c50d4673 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24Fix files with multiple newlines at the end.Martin Roth
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20704 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-06src/lib: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Idcea3f8b1a4246cb6b29999a84a191a3133e5c78 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-29lib/spd_bin: Use proper I2C addressesNico Huber
Use the plain address instead of the weird shifted encoding (e.g. if we'd use `0xa0` as address, it's actually `0x50` encoded into a write command). Change-Id: I6febb2e04e1c6de4294dfa37bde16b147a80b7a8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-27lib/coreboot_tables: Zero framebuffer structureDuncan Laurie
Zero the framebuffer structure so if it is not filled in (either if no display is present or if there is an error) then it does not provide garbage data to the payload. This was noticed when booting a board without a display attached as the payload wrote to the framebuffer at a random address. With this change the payload can properly handle the case where a display is not attached and not corrupt memory. Change-Id: I8114d88496cd2a4f2e7f07f377fe76f3180a7f40 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-06-21cr50: process uninitialized values gracefullyVadim Bendebury
The vboot code tries reading rollback protection indices from the TPM, and if the attempt to read returns TPM_E_BADINDEX, it decides that the TPM has not yet been initialized for the Chromebook use, and needs to be taken through the factory initialization sequence. TPM_E_BADINDEX is an internal representation of the TPM error 0x28b, generated on attempts to read a non existing NVMEM space. If the space exists, but has never been written the TPM returns error 0x14a. This condition (the space exists but not written) could happen if the previous factory initialization attempt was interrupted right after the space was created. Let's map this error to the same internal representation (TPM_E_BADINDEX) so that the Chrome OS device could recover when this condition occurs. BRANCH=reef, gru BUG=b:37443842 TEST=verified that the Pyro device stuck in TPM error state recovered when this patch was applied. Change-Id: I6ff976c839efcd23ae26cef3ee428e7ae02e68f8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/20299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-14Add support for Undefined Behavior SanitizerRyan Salsamendi
Initial support for undefined behavior sanitizer in ramstage. Enabling this will add -fsanitize=undefined to the compiler command line and link with ubsan.c in ramstage. Code with UB triggers a report with error, file, and line number, then aborts. Change-Id: Ib139a418db97b533f99fc59bcb1a71fb6dcd01d8 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-06-14cbmem_console: Fix undefined behaviorRyan Salsamendi
Fixes report found by undefined behavior sanitizer. Left shifting an int where the right operand is >= width of type is undefined. Add ul suffix since it's safe for unsigned types. Change-Id: I4b2365428e421085285006bc1ea8aea75890ff65 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-06-13Consolidate reset API, add generic reset_prepare mechanismJulius Werner
There are many good reasons why we may want to run some sort of generic callback before we're executing a reset. Unfortunateley, that is really hard right now: code that wants to reset simply calls the hard_reset() function (or one of its ill-differentiated cousins) which is directly implemented by a myriad of different mainboards, northbridges, SoCs, etc. More recent x86 SoCs have tried to solve the problem in their own little corner of soc/intel/common, but it's really something that would benefit all of coreboot. This patch expands the concept onto all boards: hard_reset() and friends get implemented in a generic location where they can run hooks before calling the platform-specific implementation that is now called do_hard_reset(). The existing Intel reset_prepare() gets generalized as soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now easily be added later if necessary). We will also use this central point to ensure all platforms flush their cache before reset, which is generally useful for all cases where we're trying to persist information in RAM across reboots (like the new persistent CBMEM console does). Also remove cpu_reset() completely since it's not used anywhere and doesn't seem very useful compared to the others. Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19789 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-09lib/spd_bin: Print out correct SMBus SPD address in dump_spd_infoFurquan Shaikh
With change dd82edc388 (lib/spd_bin: make SMBus SPD addresses an input), SMBus SPD addresses are accepted from the mainboard and not calculated within the spd_bin library routines. Use the addr_map values to print correct address in dump_spd_info. Change-Id: Iff37e382aeac9704f74bafc2ecb27f14c478723f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-07src: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-04lib/coreboot_tables: Remove weak fill_lb_framebuffer()Nico Huber
Remove the weak function stub fill_lb_framebuffer() and guard with the new `CONFIG_LINEAR_FRAMEBUFFER` instead. Change-Id: Ia9e477c2d501b249a632968b5636ac803323895a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-04Kconfig: Add choice of framebuffer modeNico Huber
Rename `FRAMEBUFFER_KEEP_VESA_MODE` to `LINEAR_FRAMEBUFFER` and put it together with new `VGA_TEXT_FRAMEBUFFER` into a choice. There are two versions of `LINEAR_FRAMEBUFFER` that differ only in the prompt and help text (one for `HAVE_VBE_LINEAR_FRAMEBUFFER` and one for `HAVE_LINEAR_FRAMEBUFFER`). Due to `kconfig_lint` we have to model that with additional symbols. Change-Id: I9144351491a14d9bb5e650c14933b646bc83fab0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-30lib/edid: Split out fill_lb_framebuffer()Nico Huber
Place it into new edid_fill_fb.c, and invert the logic of the Kconfig guard (NATIVE_VGA_INIT_USE_EDID is now !NO_EDID_FILL_FB). It has to be selected by all drivers that use MAINBOARD_DO_NATIVE_VGA_INIT but pro- vide their own fill_lb_framebuffer() implementation. Change-Id: I90634b835bd8e2d150b1c714328a5b2774d891bd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-27lib/spd_bin: make SMBus SPD addresses an inputAaron Durbin
Instead of assuming the mapping of dimm number to SPD SMBus address, allow the mainboard to provide its own mapping. That way, global resources of empty SPD contents aren't wasted in order to address a dimm on a mainboard that doesn't meet the current assumption. Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>