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2016-03-24edid: Add helper function to calculate bits-per-pixel dependent valuesJulius Werner
Coreboot and most payloads support three basic pixel widths for the framebuffer. It assumes 32 by default, but several chipsets need to override that value with whatever else they're supporting. Our struct edid contains multiple convenience values that are directly derived from this (and other properties), so changing the bits per pixel always requires recalculating all those dependents in the chipset code. This patch provides a small convenience wrapper that can be used to consistently update the whole struct edid with a new pixel width instead, so we no longer need to duplicate those calculations everywhere. BUG=None TEST=Booted Oak in all three pixel widths (which it conveniently all supports), confirmed that images looked good. Change-Id: I5376dd4e28cf107ac2fba1dc418f5e1c5a2e2de6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14158 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-23arch/x86: introduce postcar stage/phaseAaron Durbin
Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-22gpio: Add support for binary_first base3 number systemJulius Werner
This patch adds support for an alternative ternary number system in which group of GPIOs can be interpreted. In this system, the digit combinations that would form a binary number (i.e. that contain no 'Z' state) are used to represent the lower values in the way they're used in the normal binary system, and all the combinations that do contain a 'Z' are used to represent values above those. We can use this for boards that originally get strapped with binary board IDs but eventually require more revisions than that representation allows. We can switch their code to binary_first base3 and all old revisions with already produced boards will still get read as the correct numbers. Credit for the algorithm idea goes to Haran Talmon. BRANCH=None BUG=None TEST=Stubbed out the actual GPIO reading and simulated all combinations of 4 ternary digits for both number systems. Change-Id: Ib5127656455f97f890ce2999ba5ac5f58a20cf93 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14116 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-22lib/rmodule: export parameters in struct rmod_stage_loadAaron Durbin
In order for a caller to utilize an rmodule's parameters section after calling rmodule_stage_load() export the rmodule's parameter pointer in struct rmod_stage_load. Change-Id: I9cd51652cf8cdb3fae773256989851638aa1a60f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14139 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-21device: Add i2c read/write register field APIYidi Lin
i2c_read_field() - read the value from the specific register field i2c_write_field() - write the value to the specific register field BRANCH=none BUG=none TEST=none Change-Id: I2098715b4583c1936c93b3ff45ec330910964304 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0817fc76d07491b39c066f1393a6435f0831b50c Original-Change-Id: I92c187a89d10cfcecf3dfd9291e0bc015459c393 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332712 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14105 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-18mtrr: Define a function for obtaining free var mtrrFurquan Shaikh
Instead of hard-coding var mtrr numbers in code, use this function to identify the first available variable mtrr. If no such mtrr is available, the function will return -1. Change-Id: I2a1e02cdb45c0ab7e30609641977471eaa2431fd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14115 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-12device/i2c: Add i2c_read_bytes() APIJitao Shi
Add multi-bytes read support. BRANCH=none BUG=none TEST=saw edid log and dev screen Change-Id: I106be98e751e2a3b998ccaedb28f71f3c6e18994 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94ee0b834947e8d971943aa24e61a9353c7b7306 Original-Change-Id: Iac5fe497da92b7d09383e0d6a04d98709aea5b20 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/325211 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13978 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-10cbmem: Add utility to get memory region occupied by cbmemAlexandru Gagniuc
Change-Id: I8e57c23565f173afc0f4d450579b8bfb35aeb964 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13363 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-09lib/memrange: add function to initialize range_entryAaron Durbin
In order to enforce the semantics of struct range_entry provide an init function, range_entry_init(), which performs the field initialization to adhere to the internal struture's assumptions. Change-Id: I24b9296e5bcf4775974c9a8d6326717608190215 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13956 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-08cpu/x86/mtrr: add helper function to detect variable MTRRsAaron Durbin
The current MTRR API doesn't allow one to detect variable MTRRs along with handling fixed MTRRs in one function call. Therefore, add x86_setup_mtrrs_with_detect() to perform the same actions as x86_setup_mtrrs() but always do the dynamic detection. Change-Id: I443909691afa28ce11882e2beab12e836e5bcb3d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13935 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-03-05include/device/dram: Fix DDR3-1866Patrick Rudolph
The PLL multiplier value is off by one for DDR3-1866 due to a wrong TCK value, resulting in DDR3-1600 being used by the PLL. Needs test on real hardware ! Change-Id: I657b813889945f0d9990dd11680a3d3a25b53467 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13613 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03src/device/dram/ddr3: Parse additional informationPatrick Rudolph
Parse manufacturer id and ASCII serial. Required for SMBIOS type 17 field. Change-Id: I710de1a6822e4777c359d0bfecc6113cb2a5ed8e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13862 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02nb/intel/sandybridge/romstage: Read fuse bits for max MEM ClkPatrick Rudolph
Instead of hardcoding the maximum supported DDR frequency to 800Mhz (DDR3-1600), read the fuse bits that encode this information. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13487 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-26lib/bootblock: provide SoC callback parity with mainboardAaron Durbin
There was no 'early' call into the SoC code prior to console getting initialized. Not having this enforces the mainboard to drive the setup of the console which typically just ends up calling into the SoC code. Provide a SoC early init call to handle this without having to duplicate the same code in mainboards utilizing the same SoC. Change-Id: Ia233dc3ae89a77df284d6d5cf5b2b051ad3be089 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13791 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-22cbfs: Add LZ4 in-place decompression support for pre-RAM stagesJulius Werner
This patch ports the LZ4 decompression code that debuted in libpayload last year to coreboot for use in CBFS stages (upgrading the base algorithm to LZ4's dev branch to access the new in-place decompression checks). This is especially useful for pre-RAM stages in constrained SRAM-based systems, which previously could not be compressed due to the size requirements of the LZMA scratchpad and bounce buffer. The LZ4 algorithm offers a very lean decompressor function and in-place decompression support to achieve roughly the same boot speed gains (trading compression ratio for decompression time) with nearly no memory overhead. For now we only activate it for the stages that had previously not been compressed at all on non-XIP (read: non-x86) boards. In the future we may also consider replacing LZMA completely for certain boards, since which algorithm wins out on boot speed depends on board-specific parameters (architecture, processor speed, SPI transfer rate, etc.). BRANCH=None BUG=None TEST=Built and booted Oak, Jerry, Nyan and Falco. Measured boot time on Oak to be about ~20ms faster (cutting load times for affected stages almost in half). Change-Id: Iec256c0e6d585d1b69985461939884a54e3ab900 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13638 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-22memlayout: Add symbols for stage boundsJulius Werner
Stages are inconsistent with other memlayout regions in that they don't have _<name> and _e<name> symbols defined. We have _program and _eprogram, but that always only refers to the current stage and _eprogram marks the actual end of the executable's memory footprint, not the end of the area allocated in memlayout. Both of these are sometimes useful to know, so let's add another set of symbols that allow the stage areas to be treated more similarly to other regions. Change-Id: I9e8cff46bb15b51c71a87bd11affb37610aa7df9 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13737 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-22fsp_baytrail: Add full support for iosf access in reg_scriptWerner Zeh
Add all needed functions to fsp_baytrail so that reg_script can do full iosf access. To keep it simple, this patch synchronises iosf access between baytrail and fsp_baytrail. Change-Id: Ic7f52d7d90c0fe3560fa5a5d96f7fc15062d66d1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/13742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-22die() when attempting to use bounce buffer on non-i386.Vladimir Serbinenko
Only i386 has code to support bounce buffer. For others coreboot would silently discard part of binary which doesn't work and is a hell to debug. Instead just die. Change-Id: I37ae24ea5d13aae95f9856a896700a0408747233 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13750 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-20nb/intel/sandybridge/raminit: Add XMP supportPatrick Rudolph
Some vendors store lower frequency profiles in the regular SPD, if the SPD contains a XMP profile. To make use of the board's and DIMM's maximum supported DRAM frequency, try to parse the XMP profile and use it instead. Validate the XMP profile to make sure that the installed DIMM count per channel is supported and the requested voltage is supported. To reduce complexity only XMP Profile 1 is read. Allows my DRAM to run at 800Mhz instead of 666Mhz as encoded in the default SPD. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: Ib4dd68debfdcfdce138e813ad5b0e8e2ce3a40b2 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13486 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-19lib/coreboot_table: add function to allow arch code to add recordsAaron Durbin
Add lb_arch_add_records() to allow the architecture code to generically hook into the coreboot table generation. BUG=chrome-os-partner:50214 BRANCH=glados TEST=With all subsequent patches confirmed lb_arch_add_records() is called when a strong symbol is provided. Change-Id: I7c69c0ff0801392bbcf5aef586a48388b624afd4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13669 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-18device: Add device path display supportLee Leahy
Add an optional routine to translate the device path types into a string for display. TEST=Build and run on Galileo Change-Id: Iea5d0a2430d9a8546105324e2beda0955210dca9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13715 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18lib: Add Kconfig to toggle boot state debuggingLee Leahy
Add the DEBUG_BOOT_STATE Kconfig value to enable boot state debugging. Update include/bootstate.h and lib/hardwaremain.c to honor this value. Add a dashed line which displays between the states. Testing on Galileo: * select DEBUG_BOOT_STATE in mainboard/intel/galileo/Kconfig * Build and run on Galileo Change-Id: I6e8a0085aa33c8a1394f31c030e67ab3d5bf7299 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13716 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12lzma: Port size-checking ulzman() version to corebootJulius Werner
We've had a second version of ulzma() that would check the input and output buffer sizes in libpayload for a while now. Since it's generally never a bad idea to double-check for overruns, let's port it to coreboot and use it where applicable. (This requires a small fix in the four byte at a time read optimization we only have in coreboot, since it made the stream counter hit the end a little earlier than the algorithm liked and could trigger an assertion.) BRANCH=None BUG=None TEST=Booted Oak, Jerry and Falco. Change-Id: Id566b31dfa896ea1b991badf5a6ad9d075aef987 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13637 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-12timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION KconfigJulius Werner
This patch generalizes the approach previously used for ARM32 TTB_SUBTABLES to "auto-detect" whether a certain region was defined in memlayout.ld. This allows us to get rid of the explicit Kconfig for the TIMESTAMP region, reducing configuration redundancy and avoiding confusion when setting up future boards. (Removing armv4/bootblock_simple.c because it references this Kconfig and it is a dead file that I just forgot to remove in CL:12076.) BRANCH=None BUG=None TEST=Booted Oak and confirmed that all pre-RAM timestamps are still there. Built Nyan and Falco. Change-Id: I557a4b263018511d17baa4177963130a97ea310a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13652 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11arches: lib: add main_decl.h for main() declarationAaron Durbin
It is silly to have a single header to declare the main() symbol, however some of the arches provided it while lib/bootblock.c relied on the arch headers to declare it. Just move the declaration into its own header file and utilize it. Change-Id: I743b4c286956ae047c17fe46241b699feca73628 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13681 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-02-10cpu/intel/microcode: allow microcode to be loaded in romstageAaron Durbin
The previous usage of the intel microcode support supported using the library under ROMCC and ramstage. Allow for microcode support to be used in normal C-based romstage as well by: 1. Only using walkcbfs when ROMCC is defined. 2. Only using spinlocks if !__PRE_RAM__ The header file now unconditionally exposes the declarations of the supporting functions. Change-Id: I903578bcb4422b4c050903c53b60372b64b79af1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09nhlt: add api to override oem_id and oem_table_id of acpi_header_tFang, Yang A
This patch added nhlt_soc_serialize_oem_overrides and nhlt_serilalize_oem_overrides to be able to override oem_id and oem_table_id.board file can pass specific string by calling nhlt_soc_serialize_oem_overrides kernel use these two fields to construct a topology binary name if the designate file is not found a default dfw_sst.bin will be used it is optional. BUG=chrome-os-partner:49570 BRANCH=glados TEST=Build & Booted kunimitsu board. Verified that kernel can read new strings. Change-Id: I00b64fb8bb63de601d3116e0b8941057c1efa230 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 374ce08b2d8a2f4e5dd7f51eacb505dbb77fd171 Original-Change-Id: I03623c8ac81efb5a5ea3ec9c6cd604d2e9294022 Original-Signed-off-by: Fang, Yang A <yang.a.fang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/322860 Original-Commit-Ready: Yang Fang <yang.a.fang@intel.com> Original-Tested-by: Yang Fang <yang.a.fang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13602 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-03include/device: Move inline functions from pci_def.h to pci.hAlexandru Gagniuc
pci_def.h is supposed to only contain definitions, such that it may be included in assembly files. Declaration of functions in said file prevents that. Change-Id: I0f90a74291c8a2ef7a1e1027d2d2182f896050fb Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/13300 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-01cpu/amd/fam10h-fam15h: Add new wait_ap_stopped functionTimothy Pearson
Under certain conditions, such as when microcode updates are being performed, it is important to make sure all APs have finished updates and are halted before continuing with the boot process. Add a new wait_ap_stopped() function to allow for this functionality to be added to the appropriate mainboard romstage source files. Change-Id: Ib455c937888a58b283bd3f8fda1b486eea41b0a7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13168 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01drivers/pc80: Add PS/2 mouse presence detectTimothy Pearson
On certain Winbond SuperIO devices, when a PS/2 mouse is not present on the auxiliary channel both channels will cease to function if the auxiliary channel is probed while the primary channel is active. Therefore, knowledge of mouse presence must be gathered by coreboot during early boot, and used to enable or disable the auxiliary PS/2 port before control is passed to the operating system. Add auxiliary channel PS/2 device presence detect, and update the Winbond W83667HG-A driver to flag the auxiliary channel as disabled if no device was detected. Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13165 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Provide a gcc-safe zero pointerPatrick Georgi
zeroptr is a linker object pointing at 0 that can be used to thwart GCC's (and other compilers') "dereferencing NULL is undefined" optimization strategy when it gets in the way. Change-Id: I6aa6f28283281ebae73d6349811e290bf1b99483 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/12294 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Move object files to $(obj)/<class>/Nico Huber
Instead of tagging object files with .<class>, move them to a <class> directory below $(obj)/. This way we can keep a 1:1 mapping between source- and object-file names. The 1:1 mapping is a prerequisite for Ada, where the compiler refuses any other object-file name. Tested by verifying that the resulting coreboot.rom files didn't change for all of Jenkins' abuild configurations. Change-Id: Idb7a8abec4ea0a37021d9fc24cc8583c4d3bf67c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13181 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-01-23lib/memrange: allow stack allocated free listAaron Durbin
Instead of solely relying on malloc for building up an address space for the range_entry objects allow one to supply a list of free entries to memranges_init_empty(). Doing this and only calling malloc() in ramstage allows a memranges oboject to be used in a malloc()-free environment. Change-Id: I96c0f744fc04031a7ec228620a690b20bad36804 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13020 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-22lib: Implement framework for retrieving WiFi regulatory domainFelix Durairaj
Platforms that need to initialize WRDD package with the regulatory domain information should implement function wifi_regulatory_domain. A weak implementation is provided here. Original-Reviewed-on: https://chromium-review.googlesource.com/314384 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I84e2acd748856437b40bbf997bf23f158c711712 Signed-off-by: fdurairx <felixx.durairaj@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12744 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21memlayout: Fix unified CBFS_CACHE macroJulius Werner
commit a8aef3ac (cbfs_spi: Initialize spi_flash when initializing cbfs_cache) introduced a bug that makes the rarely-used unified CBFS_CACHE() memlayout macro break when used in conjunction with cbfs_spi.c (since that macro does not define a separate postram_cbfs_cache region). This patch fixes the problem by making all three region names always available for both the unified and split macros in every stage (and adds code to ensure we don't reinitialize the same buffer again in romstage, which might be a bad idea if previous mappings are still in use). BRANCH=None BUG=None TEST=Compiled for both kinds of macros, manually checked symbols in disassembled stages. Change-Id: I114933e93080c8eceab04bfdba3aabf0f75f8ef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f270f88e54b42afb8b5057b0773644c4ef357ef Original-Change-Id: If172d9fa3d1fe587aa449bd4de7b5ca87d0f4915 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/318834 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12933 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18header files: Fix guard name comments to match guard namesMartin Roth
This just updates existing guard name comments on the header files to match the actual #define name. As a side effect, if there was no newline at the end of these files, one was added. Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-15lib: NHLT ACPI table supportAaron Durbin
Intel's SST (Smart Sound Technology) employs audio support which may not consist of HDA. In order to define the topology of the audio devices (mics, amps, codecs) connected to the platform a NHLT specification was created to pass this information from the firmware to the OS/userland. BUG=chrome-os-partner:44481 BRANCH=None TEST=Tested on glados. Audio does get emitted and some mic recording works. Change-Id: I8a9c2f4f76a0d129be44070f09d938c28a73fd27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2472af5793dcffd2607a7b95521ddd25b4be0e8c Original-Change-Id: If469f99ed1a958364101078263afb27761236421 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312264 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12935 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07Correct some common spelling mistakesMartin Roth
- occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-06commonlib: Prepare code to be included in cbfstool builds.Aaron Durbin
Some of the files need to be adjusted so that they can be used both in cbfstool as well as coreboot proper. For coreboot, add a <sys/types.h> file such that proper types can be included from both the tools and coreboot. The other chanes are to accomodate stricter checking in cbfstool. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Built on glados including tools. Booted. Change-Id: I771c6675c64b8837f775427721dd3300a8fa1bc0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12784 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06commonlib: Add common cbfs parsing logic to coreboot and cbfstool.Aaron Durbin
To continue sharing more code between the tools and coreboot proper provide cbfs parsing logic in commonlib. A cbfs_for_each_file() function was added to allow one to act on each file found within a cbfs. cbfs_locate() was updated to use that logic. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Utilized and booted on glados. Change-Id: I1f23841583e78dc3686f106de9eafe1adbef8c9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-31imgtec/pistachio: Add SOC_REGISTERS memory regionIonela Voinescu
When used with a U-boot payload it will need this region identity mapped also, so we're defining it in preparation for that functionality. Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12768 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-29device/pnp: Ability to set vendor specific logical device configDamien Zammit
According to the PNP ISA v1.0a spec, config registers in the range of 0xf0 up to 0xfe are vendor defined and may be used for any purpose. Config register 0xff is reserved and is defined as such. Currently, only vendor specific registers 0xf0, 0xf1, 0xf4, and 0xfa are able to be set using the PNP_MSCx bit flag masks. This patch adds support for all 15 vendor specific config registers, and updates the existing superio pnp_info to use them where appropriate. Change-Id: Id43b85f74e3192b17dbd7e54c4c6136a2e59ad55 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12808 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-16lib: Fix strncmpHannah Williams
strncmp continues to compare the characters in the input strings past any null termination it may encounter. Null termination check is added. Reviewed-on: https://chromium-review.googlesource.com/314815 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Hannah Williams <hannah.williams@intel.com> Tested-by: Hannah Williams <hannah.williams@intel.com> (cherry picked from commit ca7022752115eddbcb776f0c0d778249555ddf32) Reviewed-on: https://chromium-review.googlesource.com/315130 Change-Id: Ifc378966dcf6023efe3d32b026cc89d69b0bb990 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12721 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-10lib: remove assets infrastructureAaron Durbin
Now that only CBFS access is supported for finding resources within the boot media the assets infrastructure can be removed. Remove it. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. Change-Id: I383fd6579280cf9cfe5a18c2851baf74cad004e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12690 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10cbfs/vboot: remove firmware component supportAaron Durbin
The Chrome OS verified boot path supported multiple CBFS instances in the boot media as well as stand-alone assets sitting in each vboot RW slot. Remove the support for the stand-alone assets and always use CBFS accesses as the way to retrieve data. This is implemented by adding a cbfs_locator object which is queried for locating the current CBFS. Additionally, it is also signalled prior to when a program is about to be loaded by coreboot for the subsequent stage/payload. This provides the same opportunity as previous for vboot to hook in and perform its logic. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. CQ-DEPEND=CL:307121,CL:31691,CL:31690 Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12689 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03cbfs_spi: Initialize spi_flash when initializing cbfs_cacheMary Ruthven
Most devices do not use SPI before they initialize CBMEM. This change initializes spi_flash in the CBMEM_INIT_HOOK to initialize the postram cbfs cache so it is not overwritten when boot_device_init is called later. BUG=chromium:210230 BRANCH=none TEST=confirm that the first cbfs access can occur before RAM initialized and after on panther and jerry. Change-Id: If3b6efc04082190e81c3773c0d3ce116bb12421f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ab242786a16eba7fb423694f6b266e27d7660ec Original-Change-Id: I5f884b473e51e6813fdd726bba06b56baf3841b0 Original-Signed-off-by: Mary Ruthven <mruthven@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/314311 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12601 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/fsp: Add post codes for FSP phasesDuncan Laurie
Add post codes for the various FSP phases and use them as appropriate in FSP 1.0 and 1.1 implementations. This will make it more consistent to debug FSP hangs and resets. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados and chell Change-Id: I32f8dde80a0c6c117fe0fa48cdfe2f9a83b9dbdf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3b616ff3c9d8b6d05c8bfe7f456f5c189e523547 Original-Change-Id: I081745dcc45b3e9e066ade2227e675801d6f669a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313822 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12595 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03cbfs_spi: enable CBFS access in early romstageMary Ruthven
Currently the CBFS mmap cannot be accessed at the beginning of romstage because it waits until DRAM is initialized. This change first loads CBFS into SRAM and then switches to using DRAM as the backing once it is initialized. BUG=chromium:210230 BRANCH=none TEST=confirm that the cbfs can be access at the beginning and end of romstage on different boards. Change-Id: I9fdaef392349c27ba1c19d4cd07e8ee0ac92dddc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ccaaba266386c7d5cc62de63bdca81a0cc7c4d83 Original-Change-Id: Idabfab99765b52069755e1d1aa61bbee39501796 Original-Signed-off-by: Mary Ruthven <mruthven@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312577 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12586 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-29x86/smm: don't hide harmless declarationsPatrick Georgi
Hiding them requires #if CONFIG_HAVE_SMI_HANDLER instead of if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) Change-Id: Ib874cd98e195ad7437d05be1696004b29bf97a66 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/12565 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-23southbridge/amd/sr5650: Add IOMMU supportTimothy Pearson
Change-Id: I2083d0c5653515c27d4626c62a6499b850f7547b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12044 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-23cpu/amd: de-duplicate MSR include filesStefan Reinauer
Change-Id: I8e01a4ab68b463efe02c27f589e0b4b719532eb5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12510 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-20rules.h: Add ENV_STRING and use it in console_init()Ben Gardner
Move the #ifdef chain to set the stage name to rules.h. Change-Id: I577ddf2de4ef249a1a4ce627bb55608731a9f5ed Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: http://review.coreboot.org/12479 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-17rules.h: Add ENV_ macros to detect current architectureJulius Werner
This patch expands the existing ENV_<stage> macros in <rules.h> with a set of ENV_<arch> macros which can be used to detect which architecture the current compilation unit is built for. These are more consistent than compiler-defined macros (like '#ifdef __arm__') and will make it easier to write small, architecture-dependent differences in common code (where we currently often use IS_ENABLED(CONFIG_ARCH_...), which is technically incorrect in a world where every stage can run on a different architecture, and merely kinda happened to work out for now). Also remove a vestigal <arch/rules.h> from ARM64 which was no longer used, and genericise ARM subarchitecture Makefiles a little to make things like __COREBOOT_ARM_ARCH__ available from all file types (including .ld). BUG=None TEST=Compiled Falco, Blaze, Jerry and Smaug. Change-Id: Id51aeb290b5c215c653e42a51919d0838e28621f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12433 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-11-11cpu/amd: Add CC6 supportTimothy Pearson
This patch adds CC6 power save support to the AMD Family 15h support code. As CC6 is a complex power saving state that relies heavily on CPU, northbridge, and southbridge cooperation, this patch alters significant amounts of code throughout the tree simultaneously. Allowing the CPU to enter CC6 allows the second level of turbo boost to be reached, and also provides significant power savings when the system is idle due to the complete core shutdown. Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11979 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-11arm/arm64: Generalize bootblock C entry pointJulius Werner
When we first added ARM support to coreboot, it was clear that the bootblock would need to do vastly different tasks than on x86, so we moved its main logic under arch/. Now that we have several more architectures, it turns out (as with so many things lately) that x86 is really the odd one out, and all the others are trying to do pretty much the same thing. This has already caused maintenance issues as the ARM32 bootblock developed and less-mature architectures were left behind with old cruft. This patch tries to address that problem by centralizing that logic under lib/ for use by all architectures/SoCs that don't explicitly opt-out (with the slightly adapted existing BOOTBLOCK_CUSTOM option). This works great out of the box for ARM32 and ARM64. It could probably be easily applied to MIPS and RISCV as well, but I don't have any of those boards to test so I'll mark them as BOOTBLOCK_CUSTOM for now and leave that for later cleanup. BRANCH=None BUG=None TEST=Built Jerry and Falco, booted Oak. Change-Id: Ibbf727ad93651e388aef20e76f03f5567f9860cb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-11-11southbridge/amd/sb700: Add AHCI supportTimothy Pearson
Change-Id: I147284e6a435f4b96d6821a122c1f4f9ddc2ea33 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11981 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10edid: add hdmi_monitor_detected in data struct edidYakir Yang
HDMI driver need to know whether the monitor is DVI or HDMI interface, so this commit just introduce a new number 'hdmi_monitor_detected' to struct edid. There were four bits to indicate the monitor interfaces, it's better to take use of that. But those bits only existed in EDID 1.4 version, but didn't persented in the previous EDID version, so I decided to detect the hdmi cea block. BRANCH=none BUG=chrome-os-partner:43789 TEST=When mickey connect with HDMI monitor, see 'hdmi_monitor_detected' is 'true'. When mickey connect with DVI monitor, see 'hdmi_monitor_detected' is 'false'. Change-Id: I1a4f1410e1cce1474ffae858db161a18578cac3a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 409f041805d9fdff2d49faa1a3a262cf4dc609c2 Original-Change-Id: Ife770898b0f2b4f58b8259711101a0cab4a5e4ac Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309055 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12345 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-07arm64: remove secmonAaron Durbin
It's been decided to only support ARM Trusted Firmware for any EL3 monitor. That means any SoC that requires PSCI needs to add its support for ATF otherwise multi-processor bring up won't work. Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11897 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-03drivers/pc80: Rework normal / fallback selector codeTimothy Pearson
Per IRC and Gerrit discussion, the normal / fallback selector code is a rather weak spot in coreboot, and did not function correctly for certain use cases. Rework the selector to more clearly indicate proper operation, and also remove dead code. Also tentatively abandon use of RTC bit 385; a follow-up patch will remove said bit from all affected mainboards. The correct operation of the fallback code selector approximates that of a power line recloser, with a user option to attempt normal boot that can be cleared by firmware, but never set by firmware. Additionally, if cleared by user, the fallback path should always be used on the next reboot. Change-Id: I753ae9f0710c524875a85354ac2547df0c305569 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12289 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-03cbmem: add coreboot table records for each cbmem entryAaron Durbin
In order to not expose the cbmem data structures to userland that are used by coreboot internally add each of the cbmem entries to a coreboot table record. The payload ABI uses coreboot tables so this just provides a shortcut for cbmem entries which were manually added previously by doing the work on behalf of all entries. A cursor structure and associated functions are added to the imd code for walking the entries in order to be placed in the coreboot tables. Additionally a struct lb_cbmem_entry is added that lists the base address, size, and id of the cbmem entry. BUG=chrome-os-partner:43731 BRANCH=None TEST=Booted glados. View coreboot table entries with cbmem. Change-Id: I125940aa1898c3e99077ead0660eff8aa905b13b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11757 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-11-02cpu/amd: Add initial AMD Family 15h supportTimothy Pearson
TEST: Booted ASUS KGPE-D16 with single Opteron 6380 * Unbuffered DDR3 DIMMs tested and working * Suspend to RAM (S3) tested and working Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11966 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop geode_post_code.hStefan Reinauer
It's unused and empty. Change-Id: Ieb9225083cb779b7b94ca47488dad4d7beb30a94 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12235 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30cpu/amd: Fix cbtypes.h to match UINTN conventionStefan Reinauer
There are some inconsistencies in AMDs APIs between the coreboot code and the vendorcode code. Unify the API. UINTN maps to uintptr_t in UEFI land. Do the same here. Also switch the other UEFI types to map to fixed size types. Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10601 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-27include/timer.h: Guard `timer_monotonic_get()` calls by ↵Paul Menzel
`CONFIG_HAVE_MONOTONIC_TIMER` Some platforms do not have `timer_monotonic_get()` implemented. So only call `timer_monotonic_get()` if `CONFIG_HAVE_MONOTONIC_TIMER` is selected and set the times to 0 otherwise. Change-Id: If9cba4c0c17a7011aa357079d8fdd0aa47ad1b66 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/12105 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27coreboot: make lb_framebuffer a weak functionrobbie zhang
This is to support other gfx enable method such as Gfx Peim (AKA GOP) for Intel soc. BRANCH=none BUG=chrome-os-partner:44559 TEST=Built and boot on kunimitsu/glados. Change-Id: Ib8010ea6901ea906a8b4129807b94ace71ef1165 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ad26a99560009c487070cccf6ab132188b9e247d Original-Change-Id: Id132718a8bcec5446cc4c0d9d636d26e8a99bb15 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303801 Original-Commit-Ready: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-24drivers/aspeed: Add native text mode VGA support for the AST2050Timothy Pearson
Change-Id: I37763a59d2546cd0c0e57b31fdb7aa77c2c50bee Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11937 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2015-10-24southbridge/amd/sb700: Allow use of auxiliary SMBUS controllerTimothy Pearson
Change-Id: I29ece10eeefc2c75a3829c169f1e1aede7194ec2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12079 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2015-10-23include/smbios: Update SMBIOS memory structures to version 2.8Timothy Pearson
Change-Id: Icda915933c4ebf3a735d9e1d4e4dbb1138a06b39 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11955 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins)
2015-10-22allocator: Page align memory mapped PCI resourcesNico Huber
To help hypervisors to assign PCI devices individually to virtualization guests, page align dynamically allocated MMIO resources. Tested with kontron/ktqm77 which has dynamically configured onboard devices on the root bus and secondary buses. Booted Linux and checked the configuration with `lspci -v`. Got the configuration through Muen's tools which are very picky about overlapping and alignment. Booted a Muen based system that uses many onboard devices. GMA, xHCI and one NIC (on a secondary bus) were verified to function properly. Change-Id: I2b7115070e1ccad64565feff025289732c3b5e66 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12111 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR, we also remove the _MSR suffix, as they are, by definition, MSRs. Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11761 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-11cbmem console: make verstage first class citizenAaron Durbin
The conditions in cbmem console for supporting verstage were implicitly utilizing CONFIG_BOOTBLOCK_CONSOLE to handle the cbmem console enablement. Fix it so verstage is a first class citizen for deciding actions pertaining to cbmem console. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using verstage. cbmem console shows verstage output. Change-Id: Iba79efd1c1d4056f1a105a5e10ffc95f3e69b597 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11820 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11Derive lvds_dual_channel from EDID timings.Vladimir Serbinenko
Based on the info by Felix Held. Change-Id: Iab84dd8a0e3c942da20a6e21db5510e4ad16cadd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11857 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-07cbfs: add struct cbfsfAaron Durbin
Now that cbfs is adding more metadata in the cbfs file header one needs to access that metadata. Therefore, add struct cbfsf which tracks the metadata and data of the file separately. Note that stage and payload metadata specific to itself is still contained within the 'data' portion of a cbfs file. Update the cbfs API to use struct cbfsf. Additionally, remove struct cbfsd as there's nothing else associated with a cbfs region aside from offset and size which tracked by a region_device (thanks, CBFS_ALIGNMENT!). BUG=None BRANCH=None TEST=Built and booted through end of ramstage on qemu armv7. Built and booted glados using Chrome OS. Change-Id: I05486c6cf6cfcafa5c64b36324833b2374f763c2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11679 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-05Add EM100 'hyper term' spi console support in ramstage & smmMartin Roth
The EM100Pro allows the debug console to be sent over the SPI bus. This is not yet working in romstage due to the use of static variables in the SPI driver code. It is also not working on chipsets that have SPI write buffers of less than 10 characters due to the 9 byte command/header length specified by the EM100 protocol. While this currently works only with the EM100, it seems like it would be useful on any logic analyzer with SPI debug - just filter on command bytes of 0x11. Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-30AMD Bettong: Fix usb device in devicetree for Carrizozbao
Add some missing devices to device tree and header. Remove the obsolete devices. Change-Id: Ieeca06c68fe8c8eef6be4fab43193b898aebf013 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11378 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-23chromeos: vboot and chromeos dependency removal for sw write protect statePaul Kocialkowski
This removes the dependency on chromeos and vboot for the sw write protect state function: vboot_get_sw_write_protect, renamed to get_sw_write_protect_state to both reflect this change and become consistent with the definition of get_write_protect_state that is already in use. Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-22coreboot: introduce commonlibAaron Durbin
Instead of reaching into src/include and re-writing code allow for cleaner code sharing within coreboot and its utilities. The additional thing needed at this point is for the utilities to provide a printk() declaration within a <console/console.h> file. That way code which uses printk() can than be mapped properly to verbosity of utility parameters. Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11592 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-11endian: fix le64toh()Aaron Durbin
This change was sitting in my git index, and I failed to push it in the original patch. Change-Id: If6f49c3c2b7908f93a99c23a80536ad5937959c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11622 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-10endian: add portable endian functionsAaron Durbin
The current endian API support in coreboot doesn't follow any known API that can be shared in userland as well as coreboot proper. To that end provide big and little endian helper functions that can be used in code that can be shared within coreboot proper and userland tools. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi Change-Id: I737facab0c849cb4b95756eefbf3ffd69e558b32 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11618 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-09-09rmodule: use program.ld for linkingAaron Durbin
Bring rmodule linking into the common linking method. The __rmodule_entry symbol was removed while using a more common _start symbol. The rmodtool will honor the entry point found within the ELF header. Add ENV_RMODULE so that one can distinguish the environment when generating linker scripts for rmodules. Lastly, directly use program.ld for the rmodule.ld linker script. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and analyzed the relocatable ramstage, sipi_vector, and smm rmodules. Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11517 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09verstage: use common program.ld for linkingAaron Durbin
There's no reason to have a separate verstage.ld now that there is a unified stage linking strategy. Moreover verstage support is throughout the code base as it is so bring in those link script macros into the common memlayout.h as that removes one more specific thing a board/chipset needs to do in order to turn on verstage. BUG=chrome-os-partner:44827 BRANCH=None TEST=None Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11516 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09linking: move romstage and bootblock to use program.ldAaron Durbin
Instead of having separate <stage>.ld files in src/lib one file can be used: program.ld. There's now only one touch point for stage layout. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11509 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09linking: lay the groundwork for a unified linking approachAaron Durbin
Though coreboot started as x86 only, the current approach to x86 linking is out of the norm with respect to other architectures. To start alleviating that the way ramstage is linked is partially unified. A new file, program.ld, was added to provide a common way to link stages by deferring to per-stage architectural overrides. The previous ramstage.ld is no longer required. Note that this change doesn't handle RELOCATABLE_RAMSTAGE because that is handled by rmodule.ld. Future convergence can be achieved, but for the time being that's being left out. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11507 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-09-09rules.h: add fall through where no ENV_<STAGE> is setAaron Durbin
There are cases where rules.h can be pulled in, but the usage is not associated with a particular stage. For example, the cpu/ti/am335x build creates an opmap header. That is a case where there is no stage associated with the process. Therefore, provide a case of no ENV_>STAGE> being set. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11513 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-07Drop "See file CREDITS..." commentStefan Reinauer
coreboot has no CREDITS file. Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11514 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-05symbols: add '_' to pci_drivers and cpu_drivers symbolsAaron Durbin
In order to prepare for more unification of the linker scripts prefix pci_drivers, epci_drivers, cpu_drivers, and ecpu_drivers with an underscore. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built different boards includes ones w/ and w/o relocatable ramstage. Change-Id: I8918b38db3b754332e8d8506b424f3c6b3e06af8 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11506 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-04bootstate: remove need for #ifdef ENV_RAMSTAGEAaron Durbin
The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however the current state of the header meant bad build errors in non-ramstage. Therefore, people had to #ifdef in the source. Remove that requirement. Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11492 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-04bootmode: add display_init_required()Aaron Durbin
Some of the Chrome OS boards were directly calling vboot called in some form after contorting around #ifdef preprocessor macros. The reasoning is that Chrome OS doesn't always do display initialization during startup. It's runtime dependent. While this is a requirement that doesn't mean vboot functions should be sprinkled around in the mainboard and chipset code. Instead provide one function, display_init_required(), that provides the policy for determining display initialization action. For Chrome OS devices this function honors vboot_skip_display_init() and all other configurations default to initializing display. Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11490 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-31timestamp: add tick frequency to exported tableAaron Durbin
Add the timestamp tick frequency within the timestamp table so the cbmem utility doesn't try to figure it out on its own. Those paths still exist for x86 systems which don't provide tsc_freq_mhz(). All other non-x86 systems use the monotonic timer which has a 1us granularity or 1MHz. One of the main reasons is that Linux is reporting /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq as the true turbo frequency on turbo enables machines. This change also fixes the p-state values honored in cpufreq for turbo machines in that turbo p-pstates were reported as 100MHz greater than nominal. BUG=chrome-os-partner:44669 BRANCH=firmware-strago-7287.B TEST=Built and booted on glados. Confirmed table frequency honored. Change-Id: I763fe2d9a7b01d0ef5556e5abff36032062f5801 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11470 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-28edid: add function to manually specify modeDavid Hendricks
This patch will let you to choose a favourite mode to display, while not just taking the edid detail timing. But not all modes are able to set, only modes that are in established or standard timing, and we only support a few common common resolutions for now. BUG=chrome-os-partner:42946 BRANCH=firmware-veyron TEST=tested dev mode on Mickey at 640x480@60Hz Change-Id: I8a9dedfe08057d42d85b8ca129935a258cb26762 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 090583f90ff720d88e5cfe69fcb2d541c716f0e6 Original-Change-Id: Iaa8c9a6fad106ee792f7cd1a0ac77e3dcbadf481 Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com> Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289671 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11390 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28edid: Use edid_mode struct to reduce redundancyDavid Hendricks
This replaces various timing mode parameters parameters with an edid_mode struct within the edid struct. BUG=none BRANCH=firmware-veyron TEST=built and booted on Mickey, saw display come up, also compiled for link,falco,peppy,rambi,nyan_big,rush,smaug [pg: extended to also cover peach_pit, daisy and lenovo/t530] Change-Id: Icd0d67bfd3c422be087976261806b9525b2b9c7e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: abcbf25c81b25fadf71cae106e01b3e36391f5e9 Original-Change-Id: I1bfba5b06a708d042286db56b37f67302f61fff6 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289964 Original-Reviewed-by: Yakir Yang <ykk@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28edid: Clean-up the edid structDavid Hendricks
There are serveral members of the edid struct which are never used outside of the EDID parsing code itself. This patch moves them to a struct in edid.c. They might be useful some day but until then we can just pretty print them and not pollute the more general API. BUG=none BRANCH=firmware-veyron TEST=compiled for veyron_mickey, peppy, link, nyan_big, rush, smaug Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I660f28c850163e89fe1f59d6c5cfd6e63a56dda0 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: ee8ea314a0d8f5993508f560fc24ab17604049df Original-Change-Id: I7fb8674619c0b780cc64f3ab786286225a3fe0e2 Original-Reviewed-on: https://chromium-review.googlesource.com/290333 Original-Reviewed-by: Yakir Yang <ykk@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/11387 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-27stdlib: don't hide the malloc et all declarationsAaron Durbin
It doesn't hurt to expose declarations. Instead of a compile-time error there'll be a link error if someone tries to malloc() anything. Change-Id: Ief6f22c168c660a6084558b5889ea4cc42fefdde Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11406 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-08-14stage_cache: make prog const in stage_cache_add()Aaron Durbin
The stage_cache_add() function should not be manipulating the struct prog argument in anyway. Therefore, mark it as const. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I4509e478d3c98247b9d776f6534b949d9ba6282c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290721 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ibadc00a9e1cbbf12119def92d77a79077625fb85 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11192 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-29Add SoC specific microcode update check in ramstageRizwan Qureshi
Some Intel SoCs which support SGX feature, report the microcode patch revision one less than the actual revision. This results in the same microcode patch getting loaded again. Add a SoC specific check to avoid reloading the same patch. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:286054 Change-Id: Iab4c34c6c55119045947f598e89352867c67dcb8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ab2ed73db3581cd432f9bc84acca47f5e53a0e9b Original-Change-Id: I4f7bf9c841e5800668208c11b0afcf8dba48a775 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287513 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11055 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-23intel/common: Add SMBIOS memory widthLee Leahy
Add SMBIOS symbols to define the memory width. Update the Intel common code to display the memory width and provide the memory width to SMBIOS. Also display the memory frequency, size and bus width in decimal. BRANCH=none BUG=None TEST=None Change-Id: I67b814d79fdbbf6ce65ac6b4a8282ab15fb91369 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0e59c7260afd180f3adcbeda7cef1b9eca3ed846 Original-Change-Id: Ibd26812c2aad4deaab62111b1e018be69c4faa7b Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282115 Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11032 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-22lib/hexdump: Add xxd hintLee Leahy
For people new to Linux, add the xxd hint to compare output with output from Linux. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: Ia46aeed056b12abbadf8205b044944385d9410e1 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-15cbfs: hardcode file alignmentPatrick Georgi
Assume that it's 64 byte. Change-Id: I168facd92f64c2cf99c26c350c60317807a4aed4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10919 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-14cbtable: describe boot mediaPatrick Georgi
This allows finding the currently used CBFS (in case there are several), and avoids the need to define flash size when building the payload. Change-Id: I4b00159610077761c501507e136407e9ae08c73e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10867 Tested-by: build bot (Jenkins)