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AgeCommit message (Expand)Author
2012-04-04Add support to run SMM handler in TSEG instead of ASEGStefan Reinauer
2012-04-03Add support for Intel Turbo Boost featureStefan Reinauer
2012-04-03smbios: add support for onboard devices extended informationStefan Reinauer
2012-04-02Add a helper function to determine the number of enabled CPUsStefan Reinauer
2012-04-02Align: Make sure 1 is treated as unsigned long instead of intStefan Reinauer
2012-03-30Make MTRR min hole alignment 64MBDuncan Laurie
2012-03-30Add more timestamps in coreboot.Stefan Reinauer
2012-03-30Add timestamps for selfboot and acpi wakeDuncan Laurie
2012-03-30Add TPM support to corebootStefan Reinauer
2012-03-30Add an option to keep the ROM cached after romstageStefan Reinauer
2012-03-29Add infrastructure for global data in the CAR phase of bootGabe Black
2012-03-29Detect whether the OXPCIE card is really present while in the ROM stage.Gabe Black
2012-03-29Add support for enabling PCIe Common Clock and ASPMDuncan Laurie
2012-03-29Refactor publishing CBMEM addresses through coreboot table.Vadim Bendebury
2012-03-29Add timestamp table pointer to the coreboot table.Vadim Bendebury
2012-03-29CBMEM CONSOLE: Add CBMEM type for console buffer.Vadim Bendebury
2012-03-29CBMEM CONSOLE: Add CBMEM console driver implementation.Vadim Bendebury
2012-03-29Increase CBMEM to accommodate larger console.Vadim Bendebury
2012-03-28Add cmos helper functions for reading/writing a dwordDuncan Laurie
2012-03-28Add timestamp collecting to coreboot.Vadim Bendebury
2012-03-28Initialize CBMEM early.Vadim Bendebury
2012-03-27Add RDC R8610 PCI IDs.Rudolf Marek
2012-03-16xchg is atomic with side-effectsPatrick Georgi
2012-03-14Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is availableGabe Black
2012-03-09Increase size of the coreboot table areaStefan Reinauer
2012-03-09Add helper function to find a Local APIC by ID in the device tree.Duncan Laurie
2012-03-09move console includes to central console/console.hStefan Reinauer
2012-03-09Add an implementation for the memchr library functionGabe Black
2012-03-08Unify Local APIC address definitionsPatrick Georgi
2012-02-16pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci idsKerry Sheh
2012-02-16AGESA F15: AGESA family15 model 00-0fh cpu wrapperKerry Sheh
2012-02-13AMD Geode cpus: apply un-written naming rulesKyösti Mälkki
2012-02-07Add OPROM mapping support to corebootStefan Reinauer
2012-01-24RD890: pci_ids updateKerry Sheh
2012-01-23post code: Replaced hard-coded post code with macroVikram Narayanan
2012-01-12lib: add ram_check_nodieSven Schnelle
2012-01-10MTRR: get physical address size from CPUIDSven Schnelle
2011-12-13Fix CMOS handling for non-USE_OPTION_TABLE configurationPatrick Georgi
2011-11-01remove trailing whitespaceStefan Reinauer
2011-11-01Remove XIP_ROM_BASEPatrick Georgi
2011-10-31Fix usb debug dongle supportSven Schnelle
2011-10-28Get rid of AUTO_XIP_ROM_BASEPatrick Georgi
2011-10-21Extend coreboot table entry for serial portsStefan Reinauer
2011-10-21Add macros for 64bit byte order swappingStefan Reinauer
2011-10-13Enable/fix compilation of i8254 code in ram stage.Stefan Reinauer
2011-10-12SB800: Sata Enable bus master and enable ahci for AHCI/RAID modeKerry Sheh
2011-10-03pci_ids: Add sb800 SATA device raid mode device idKerry Sheh
2011-09-15Build warning fix for AMD Family 12efdesign98
2011-09-12Miscellaneous AMD F14 warning fixesefdesign98
2011-09-07Add support for the tracing infastructure in coreboot.Rudolf Marek
2011-08-26Add automatic SMBIOS table generationSven Schnelle
2011-08-18export get_cbfs_header()Sven Schnelle
2011-08-04split CBFS support into shared core and extended functionsPatrick Georgi
2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
2011-07-13Make AMD SMM SMP awareRudolf Marek
2011-07-12Do full flush on uart8250 only at end of printk.Kevin O'Connor
2011-06-28Addition of Family12/SB900 wrapper codeefdesign98
2011-06-28SMM: add guard and include types.h in cpu/x86/smm.hSven Schnelle
2011-06-15SMM: don't overwrite SMM memory on resumeSven Schnelle
2011-06-15CMOS: add set_option()Sven Schnelle
2011-06-07SMM: add defines for APM_CNT registerSven Schnelle
2011-06-06SMM: add mainboard_apm_cnt() callbackSven Schnelle
2011-06-03Correct wrong PCI ID for VIA K8M890 Chrome.Alexandru Gagniuc
2011-05-15Cosmetic cleanup.Scott Duplichan
2011-05-15Enable AHCI mode and hide IDE controller to reduce boot time.Scott Duplichan
2011-05-10Change read_option() to a macro that wraps some API uglynessPatrick Georgi
2011-05-09Adds RS740 HT and internal graphics PCI ids.Ivaylo Valkov
2011-04-26Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as anStefan Reinauer
2011-04-22The UART divider should be calculated based on the base frequencyStefan Reinauer
2011-04-21more ifdef -> if fixesStefan Reinauer
2011-04-21some ifdef --> if fixesStefan Reinauer
2011-04-20Simplify coreboot's console/console.hStefan Reinauer
2011-04-20pci1x2x: add PCI1510 device IDsSven Schnelle
2011-04-20drop dead uart init code.Stefan Reinauer
2011-04-11Unify use of post_codeAlexandru Gagniuc
2011-04-10In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.Stefan Reinauer
2011-03-27Add AMD SR56x0 support.Zheng Bao
2011-03-01Fix a simple whitespace error in src/include/device/device.hSven Schnelle
2011-03-01Add subsystemid option to sconfigSven Schnelle
2011-02-16Extended K8T890 driver to include the K8T800 and K8M800 northbridgesAlexandru Gagniuc
2011-02-14I missed a file that was part of the AMD AGESA CPU wrapper checkin, r6347.Frank Vibrans
2011-02-03Wrap CONFIG_MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID in weak functionsPatrick Georgi
2011-01-31Add PCI ID's for VIA K8T800 and K8M800 northbridges.Alexandru Gagniuc
2011-01-28This patch gets usbdebug console working in romstage.Stefan Reinauer
2011-01-19Revert r5902 to make code more readable again. At least three people like toStefan Reinauer
2011-01-19Now that the VIA code is run above 1Meg (like other boards), it shouldKevin O'Connor
2011-01-18Move option table (cmos.layout's binary representation)Patrick Georgi
2011-01-01Add AMD SB800 southbridge support via cimx_wrapper.Kerry She
2010-12-31Add RS785(RS880) support. Just few pci_ids.Zheng Bao
2010-12-29-Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)Nils Jacobs
2010-12-26Replace Geode GX2 MSR addresses for GLCP on GLIU1 with namesNils Jacobs
2010-12-26Clean up Geode GX2 comments, whitespace and coding style. Trivial.Nils Jacobs
2010-12-18SMM for AMD K8 Part 1/2Stefan Reinauer
2010-12-17fix the tree again. Stefan Reinauer
2010-12-17drop one more version of doing serial uart output differently.Stefan Reinauer
2010-12-17guard against the case that CONFIG_WAIT_BEFORE_CPUS_INIT is not defined at all.Stefan Reinauer
2010-12-13Compile cbmem.c instead of including it in romstage,Rudolf Marek
2010-12-13We hardcode highmemory size in every northbridge! This is bad, and especiall...Rudolf Marek
2010-12-11Following patch makes just one fadt.c file. For SB700.Rudolf Marek
2010-12-11factor out cpu power management base into a separate file. And fix a bug inStefan Reinauer
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