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The CS42L42 low power audio codec can be connected over SoundWire and
be configured for mainboards to use:
- Data Port 0 and Bulk Register Access
- Data Port 1 is the 64bit data output for the headset
- Data Port 2 is the 64bit data input for the headset
- Data Port 3 is the 64bit data input for the headset
The data port and audio mode properties are filled out as best as
possible with the datasheet as a reference.
The ACPI address for the codec is calculated with the information in
the codec driver combined with the devicetree.cb hierarchy where the
link and unique IDs are extracted from the device path.
For example this device is connected to master link ID 0 and has strap
settings configuring it for unique ID 0.
chip drivers/soundwire/cs42l42
register "desc" = ""Headset Codec""
device generic 0.0 on end
end
This driver was tested with the rex0 reference design by booting
and disassembling the runtime SSDT to ensure that the devices have the
expected address and properties.
Device (SW00)
{
Name (_ADR, 0x00001001FA424200) // _ADR: Address
Name (_DDN, "Headset Codec") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
GpioInt (Edge, ActiveBoth, Exclusive, PullDefault, 0x0000,
"\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x0166
}
GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
"\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x0167
}
})
Name (_DSD, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "irq-gpios",
Package () { \_SB.PCI0.HDAS.SNDW.SW00, Zero, Zero, Zero }
},
Package () { "reset-gpios",
Package () { \_SB.PCI0.HDAS.SNDW.SW00, One, Zero, Zero }
},
Package () { "cirrus,ts-inv", One },
Package () { "cirrus,ts-dbnc-rise", 0x05 },
Package () { "cirrus,ts-dbnc-fall", Zero },
Package () { "cirrus,btn-det-init-dbnce", 0x64 },
Package () { "cirrus,btn-det-event-dbnce", 0x0A },
Package () { "cirrus,bias-lvls",
Package () { 0x0F, 0x08, 0x04, One }
},
Package () { "cirrus,hs-bias-ramp-rate", 0x02 },
Package () { "cirrus,hs-bias-sense-disable", One },
Package () { "mipi-sdw-sw-interface-revision", 0x00010000 },
[...]
Package () { "mipi-sdw-source-port-list", 0x02 },
Package () { "mipi-sdw-sink-port-list", 0x0C }
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-bra-mode-0", "BRA0" },
Package () { "mipi-sdw-dp-0-subproperties", "DP0" },
Package () { "mipi-sdw-port-audio-mode-0", "MOD0" },
Package () { "mipi-sdw-dp-1-source-subproperties", "SRC1" },
Package () { "mipi-sdw-dp-2-sink-subproperties", "SNK2" },
Package () { "mipi-sdw-dp-3-sink-subproperties", "SNK3"}
}
})
Name (BRA0, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-bra-mode-bus-frequency-configs",
Package () { 0x00AC4400, ... }
},
Package () { "mipi-sdw-bra-mode-max-data-per-frame", 0x1000 },
Package () { "mipi-sdw-bra-mode-min-us-between-transactions", Zero }
}
})
Name (DP0, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-port-max-wordlength", 0x40 },
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-bra-mode-0", "BRA0" }
}
})
Name (MOD0, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-audio-mode-bus-frequency-configs",
Package () { 0x00AC4400, ... }
},
Package () { "mipi-sdw-audio-mode-max-sampling-frequency", 0x0002EE00 },
Package () { "mipi-sdw-audio-mode-min-sampling-frequency", 0x1F40 },
[...]
}
})
Name (SRC1, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-data-port-type", Zero },
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }
}
})
Name (SNK2, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-data-port-type", Zero },
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }
}
})
Name (SNK3, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-data-port-type", Zero },
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }
}
})
}
BUG=b:269497731
TEST=Verified SSDT for SNDW in the OS
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ic7cfe2a21c76ba01ad3dea2a5017b28743aeb9f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73279
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The MAX98363 smart speaker amp can be connected over SoundWire and be
configured for mainboards to use:
- Data Port 0 and Bulk Register Access is not supported
- Data Port 1 is the 32bit data input for the speaker path
The data port and audio mode properties are filled out as best as
possible with the datasheet as a reference.
The ACPI address for the codec is calculated with the information in
the codec driver combined with the devicetree.cb hierarchy where the
link and unique IDs are extracted from the device path.
For example this device is connected to master link ID 2 and has strap
settings configuring it for unique ID 0.
chip drivers/soundwire/max98363
register "desc" = ""Left Speaker Amp""
device generic 2.0 on end
end
This driver was tested with the rex0 reference design by booting
and disassembling the runtime SSDT to ensure that the devices have the
expected address and properties.
Device (SW20)
{
Name (_ADR, 0x000230019F836300) // _ADR: Address
Name (_DDN, "Left Speaker Amp") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_DSD, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-sw-interface-revision", 0x00010000 },
[...]
Package () { "mipi-sdw-source-port-list", Zero },
Package () { "mipi-sdw-sink-port-list", 0x02 }
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-audio-mode-0", "MOD0" },
Package () { "mipi-sdw-dp-1-sink-subproperties", "SNK1" }
}
})
Name (MOD0, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-audio-mode-bus-frequency-configs",
Package () { 0x00927C00, ... }
},
Package () { "mipi-sdw-audio-mode-sampling-frequency-configs",
Package () { 0x3E80, ... }
},
[...]
}
})
Name (SNK1, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () { "mipi-sdw-data-port-type", Zero },
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package ()
{
Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }
}
})
}
BUG=b:269497731
TEST=Verified SSDT for SNDW in the OS
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ie56109d615759e3e5e32782c8782cb2f47014ec4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73278
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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