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2021-10-21include/memory_info.h: Increase DIMM_INFO_TOTAL number from 8 to 16Tim Chu
Increase the number of total dimm to 16 to support system with more than 8 dimms. Also, remove unneeded comment. TESTED=On S9S, dmidecode -t 17 shows expected results. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Iead53e96f37c55ba1b7a13fb62db1a1c10fa2e1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58440 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01memory_info.h: Store SMBIOS error correction typeAngel Pons
There are platforms that support error correction types other than single-bit ECC. Extend meminfo to accomodate additional ECC types. It is assumed that `struct memory_info` is packed to save space. Thus, use `uint8_t` instead of an enum type (which are usually 4 bytes wide). Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc: move mainboard_get_dram_part_num prototype to memory_info.hNick Vaccaro
BUG=b:169774661, b:168724473 TEST="emerge-volteer coreboot && emerge-nocturne coreboot && emerge-dedede coreboot" and verify they build successfully. Change-Id: I8b228475621ca1035fe13f8311355fc3b926e897 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-03memory_info: add max_speed_mts and configured_speed_mtsRob Barnes
ddr_frequency is ambiguous and is interpreted differently in several places. Instead of renaming this field, this deprecates it and adds two new fields with unambiguous naming, max_speed_mts and configured_speed_mts. smbios.c falls back to using ddr_frequency when either of these fields are 0. The same value was being used for both configured memory speed and max memory speed in SMBIOS type 17, which is not accurate when configured speed is not the max speed. BUG=b:167218112 TEST=Boot ezkinil, no change to dmidecode -t17 Change-Id: Iaa75401f9fc33642dbdce6c69bd9b20f96d1cc25 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44549 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30smbios: Fix type 17 for Windows 10Patrick Rudolph
The `GetPhysicallyInstalledSystemMemory` API call, at least on Windows 10, returns an error if SMBIOS tables are invalid. Various tools use this API call and don't operate correctly if this fails. For example, the "Intel Processor Diagnostic Tool" program is affected. Windows then guesses the physical memory size by accumulating entries from the firmware-provided memory map, which results in a total memory size that is slightly lower than the actual installed memory capacity. To fix this issue, add the handle to a type 16 entry to all type 17 entries. Add new fields to struct memory_info and fill them in Intel common code. Use the introduced variables to fill type 16 in smbios.c and provide a handle to type 17 entries. Besides keeping the current behaviour on intel/soc/common platforms, the type 16 table is also emitted on platforms that don't explicitly fill it, by using the existing fields of struct memory_info. Tested on Windows 10: The GetPhysicallyInstalledSystemMemory API call doesn't return an error anymore and the installed memory is now being reported as 8192 MiB. Change-Id: Idc3a363cbc3d0654dafd4176c4f4af9005210f42 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: move copyrights and authors to AUTHORSPatrick Georgi
Also split "this is part of" line from copyright notices. Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-06src/soc/intel/common/smbios: Add addtional infos to dimm_infoChristian Walter
Add ECC Support and VDD Voltage to dimm_info struct. Now Bus Width and ECCSupport will be propagated correctly in SMBIOS Type 17 Entry. Change-Id: Ic6f0d4b223f1490ec7aa71a6105603635b514021 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33031 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16SMBIOS: Remove duplicated smbios_memory_type enumElyes HAOUAS
Change-Id: I49554d13f1b6371b85a58cc1263608ad9e99130e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-10lib: increase part number size in memory_info/dimm_infoAaron Durbin
The dimm_info and memory_info structs are used in devices that don't strictly use DIMMs. Those platforms have the DRAM soldered down so there's no DIMM part number that encapsulates the DRAMs used in the DIMM. The full part number is desired to be exposed in the SMBIOS tables. As such extend DIMM_INFO_PART_NUMBER_SIZE to 33 to accommodate longer part numbers 'MT53B256M32D1NP-053 WT:C' is one of the longer part numbers that are desired to be maintained. BUG=b:115697578 Change-Id: I0c39dd1d1c2f0776d70d8c4d8d56719779ff82ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-24include/memory_info.h: Change part number field from 19 bytes to 21Richard Spiegel
DDR4 reserves 20 bytes for part number without termination. Therefor coreboot buffer for part number has to be increased to 21 bytes, to account termination. BUG=b:77943312 TEST=Build kahlee. Change-Id: I57aa8e06d907a1e6b11ce88f612a0d6c14b7c65b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-12include/memory_info.h: Change serial number field from 5 bytes to 4Raul E Rangel
dimm_info.serial had a strange contract. The SPD spec defines a 4 byte serial number. dimm_info.serial required a 4 character ascii string with a null terminator. This change makes the serial field so it matches the SPD spec. smbios.c will then translate the byte array into hex and set it on the smbios table. There were only two callers that set the serial number: * haswell/raminit.c: already does a memcpy(serial, spd->serial, 4), so it already matches the new contract. * amd_late_init.c: Previously copied the last 4 characters. Requires decoding the serial number into a byte array. google/cyan/spd/spd.c: This could be updated to pass the serial number, but it uses a hard coded spd.bin. Testing this on grunt, dmidecode now shows the full serial number: Serial Number: 00000000 BUG=b:65403853 TEST=tested on grunt Change-Id: Ifc58ad9ea4cdd2abe06a170a39b1f32680e7b299 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/25343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-23include: Update dimm_info documentationRaul E Rangel
Reference the JEDEC SPD spec and clarify some comments. BRANCH=dimm-info BUG=b:65403853 TEST=Documentation change only Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1f2a3a70919c34f17472904323ec5accdfc876be Reviewed-on: https://review.coreboot.org/25301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-26src/arch/x86/smbios.c: Fix type 17 part numberRichard Spiegel
Some DIMMs have invalid strings when it comes to device part number (bytes 0x149-0x15c). From DDR4 SPD specs it should be ASCIIZ with unused space filled with white spaces (ASCII 0x20). Byte 20 should be 0 (ASCIIZ), all others should be ASCII. Create a test that detects invalid strings and replace invalid characters with *. If a replacement was made the output string then must be <Invalid (replaced string)>. BUG=b:73122207 TEST=Build, boot and record serial output for kahlee while injecting different strings to dmi17->PartNumber. Use code to examine SMBIOS, while testing different valid and invalid strings. Remove string injection before committing. Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-01src/include: Include stdint.h since struct dimm_info uses itBarnali Sarkar
struct dimm_info has all the parameter types defined in stdint.h file. So including it. BUG=none BRANCH=none TEST=Build and boot KBLRVP Change-Id: I707523749ecf415e993b460f9613eae7be859c34 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18471 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-03-27smbios: add funtion for smbios type17Kane Chen
Add smbios type 17 which can optionally be implemented at the platform or mainboard level In order to create SMBIOS type17, you will need to fill memory_info data BUG=None BRANCH=None TEST=Compile successfully on rambi and samus Boot to chromeOS on samus and rambi Original-Change-Id: Ie4da89135c879d7a687305d423103fcfcbb96e3f Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210005 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 634b899ba41242caa800d7b570f3a339c738db77) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I61d1e8b1d32d43f0011b0f93966d57646ea0eb63 Reviewed-on: http://review.coreboot.org/8955 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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