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path: root/src/include/device/pci_ops.h
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2018-05-02pci: Fix MMCONF_SUPPORT on non x86Patrick Rudolph
Move x86 specific pci_bus_default_ops into arch/x86 folder. Fixes compilation on platforms that do neither have MMCONF_SUPPORT nor NO_MMCONF_SUPPORT (for example: all non-x86) but select PCI. Change-Id: I0991ab00c9a56b23cd012dd2b8b861f9737a9e9c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2016-12-06PCI ops: Remove pci_mmio_xx() in ramstageKyösti Mälkki
MMCONF operations are already the default so these would never be used. Change-Id: I671f3d2847742e400bc4ecfccc088e3b79d43070 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17691 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2014-11-05pci_ops.{c,h}: Don't hide pointers behind typedefsEdward O'Callaghan
Change-Id: I7cf7c236f94314d7970b19063d73db788c8267e5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7227 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2013-08-01Add directive __SIMPLE_DEVICE__Kyösti Mälkki
The tests for __PRE_RAM__ or __SMM__ were repeatedly used for detection if dev->ops in the devicetree are not available and simple device model functions need be used. If a source file build for ramstage had __PRE_RAM__ inserted at the beginning, the struct device would no longer match the allocation the object had taken. This problem is fixed by replacing such cases with explicit __SIMPLE_DEVICE__. Change-Id: Ib74c9b2d8753e6e37e1a23fcfaa2f3657790d4c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3555 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-05PCI Type2 config must dieRonald G. Minnich
PCI Type 2 config was a strange and never-used config mechanism. It is unlikely that in the 13 years of coreboot's existence that type 2 was ever used; it just made life complicated for everyone. It lived long enough in coreboot to be replaced by mmioconf. Prior to making the device tree visible in romstage we want to get rid of type2. Delete two files we don't need any more (yay!). Replace two functions with one: pci_config_default, which returns a pointer to the default config method. At some future time this may change to mmio but for now it is old type1 style. Change-Id: Icc4ccf379a89bfca8be43f305b68ab45d88bf0ab Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1159 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2010-11-04Various cosmetic and coding style fixes in src/devices.Uwe Hermann
Also: - Improve a few code comments, fix typos, etc. - Change a few more variable types to u8/u16/u32 etc. - Make some very long lines fit into 80chars/line. - Drop a huge duplicated comment, use "@see" to refer to the other one. - Reduce nesting level a bit by restructuring some code chunks. - s/Config.lb/devicetree.cb/ in a few places. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22If no pci access method has been set for the device tree so far (e.g.Carl-Daniel Hailfinger
during early coreboot_ram), pci_{read,write}_config{8,16,32} will die(). This patch changes pci_{read,write}_config{8,16,32} to use the existing PCI access method autodetection infrastructure instead of die()ing. Until r4340, any usage of pci_{read,write}_config{8,16,32} in coreboot_ram before the device tree was set up resulted in either a silent hang or a NULL pointer dereference. I changed the code in r4340 to die() properly with a loud error message. That still was not perfect, but at least it allowed people to see why their new ports died. Still, die() is not something developers like to see, and thus a patch to automatically pick a sensible default instead of dying was created. Of course, handling PCI access method selection automatically for fallback purposes has certain limitations before the device tree is set up. We only check if conf1 works and use conf2 as fallback. No further tests are done. This patch enables cleanups and readability improvements in early coreboot_ram code: Without this patch: dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x64); With this patch: dword = pci_read_config32(sm_dev, 0x64); Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30This patch unifies the use of config options in v2 to all start with CONFIG_Stefan Reinauer
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06Fix mmconf (PCIe memory mapped config space access) support in v2. It wasStefan Reinauer
horribly broken and thus never used by any platform. This needs to get straightened out so current chipsets drivers can use the full feature set. Create wrapper functions similar to the io pci config space ones. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04- Update abuild.sh so it will rebuild successfull buildsEric Biederman
- Move pci_set_method out of hardwaremain.c - Re-add debugging name field but only include the CONFIG_CHIP_NAME is enabled. All instances are now wrapped in CHIP_NAME - Many minor cleanups so most ports build. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-12- Modify the freebios tree so the pci config space api is mostly in sync betweenEric Biederman
code that runs without ram and code that runs with ram. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-24- Small step forward Linux boots and almost works...Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1