summaryrefslogtreecommitdiff
path: root/src/include/device/pci.h
AgeCommit message (Collapse)Author
2014-05-29PCI IRQs: Swizzle PCI IRQs for PCI bridgesMike Loptien
The PCI Specification states that devices that implement a bridge and a secondary bus must swizzle (rotate) the interrupt pins according to the table below: Child Dev # Child PIN Parent PIN 0,4,8,12... A/B/C/D A/B/C/D 1,5,9,13... A/B/C/D B/C/D/A 2,6,10,14.. A/B/C/D C/D/A/B 3,7,11,15.. A/B/C/D D/A/B/C Which is also described by this equation: PIN_parent = (Pin_child + Dev_child) % 4 When a device is found and its bus number is greater than 0, it is on a bridge and needs to be swizzled. Following the string of parents up to the root bus and swizzling as we go gives us the desired swizzling result. When BIOS_SPEW is defined, it will print out each step of the swizzling process. Change-Id: Icafeadd01983282c86e25f560c831c9482c74e68 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/5734 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
2014-04-18build rules: Identify build stage with simple variablesKyösti Mälkki
Provide simple environment variables telling which stage of boot is being built. Also move this to arch-agnostic location. Change-Id: I8cbb5cf91f53e01c06e7d672b5be3f5c235f911d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5410 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-04-09OxPCIe uart: Split PCI bridge controlKyösti Mälkki
None of the PCI bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid, fill samsung/lumpy with working values. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5237 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-12PCI: Add capability list parser to romstageKyösti Mälkki
These are almost one-to-one copies from pci_device.c. However, devicetree has not been enumerated yet and we have no console. Change-Id: Ic80c781626521d03adde05bdb1916acce31290ea Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5196 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-12PCI: Guard pci.h with CONFIG_PCIKyösti Mälkki
Adding PCI functions for romstage in pci.h breaks ARMv7 build without this. Also fix two related includes to use pci_def.h instead. Change-Id: I5291eaf6ddf5a584f50af29cf791d2ca4d9caa71 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5199 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24Add test to match struct device with pci_devfn_tKyösti Mälkki
Add a function to test if pci_devfn_t matches with a device instance of struct device, by comparing bus:dev.fn. Change-Id: Ic6c3148ac62c7183246d83302ee504b17064c794 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3474 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-01Add directive __SIMPLE_DEVICE__Kyösti Mälkki
The tests for __PRE_RAM__ or __SMM__ were repeatedly used for detection if dev->ops in the devicetree are not available and simple device model functions need be used. If a source file build for ramstage had __PRE_RAM__ inserted at the beginning, the struct device would no longer match the allocation the object had taken. This problem is fixed by replacing such cases with explicit __SIMPLE_DEVICE__. Change-Id: Ib74c9b2d8753e6e37e1a23fcfaa2f3657790d4c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3555 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-25Redefine pci_bus_default_ops as functionKyösti Mälkki
Taking device_t as a parameter, this allows to alter the PCI config access handlers. This is useful to add tracing of PCI config writes for devices having problems to initialise correctly. On older AMD platform PCI MMIO may not be able to fully configure all PCI devices/nodes, while MMIO_SUPPORT_DEFAULT would be preferred due to its atomic nature. So those can be forced to IO config instead. Change-Id: I2162884185bbfe461b036caf737980b45a51e522 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3608 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-11pci.h: Drop unused `mainboard_pci_subsystem*` prototypesPatrick Georgi
We used to allow mainboards to override subsystems using mainboard_pci_subsystem_vendor_id and mainboard_pci_subsystem_device_id. Mechanisms have changed and the only occurrence of these names is in the header. Change-Id: Ic2ab13201a2740c98868fdf580140b7758b62263 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2625 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2012-08-04Make the device tree available in the rom stageStefan Reinauer
We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1398 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-05PCI Type2 config must dieRonald G. Minnich
PCI Type 2 config was a strange and never-used config mechanism. It is unlikely that in the 13 years of coreboot's existence that type 2 was ever used; it just made life complicated for everyone. It lived long enough in coreboot to be replaced by mmioconf. Prior to making the device tree visible in romstage we want to get rid of type2. Delete two files we don't need any more (yay!). Replace two functions with one: pci_config_default, which returns a pointer to the default config method. At some future time this may change to mmio but for now it is old type1 style. Change-Id: Icc4ccf379a89bfca8be43f305b68ab45d88bf0ab Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1159 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-05-01Allow device ID arrays in the PCI driver structureVadim Bendebury
Many PCI devices share the very same driver despite having different PCI device IDs, which causes a lot of copy and paste of driver definitions. This change introduces a way to specify the array of acceptable device IDs in a single driver entry. As an example the Intel {Sandy|Ivy} Bridge SATA driver is being modified to use a single driver structure for all different SATA controller flavors, a few more Ivy Bridge IDs are being added as well. BUG=none TEST=manual . modified coreboot brought up an Ivy Bridge platform all the way to Linux login screen. Change-Id: I761c5611b93ef946053783f7a755e6c456dd6991 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/982 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-02-03Wrap CONFIG_MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID in weak functionsPatrick Georgi
This is so that boards can determine them on runtime based on hardware properties, if so desired. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Joseph Kellermann <Joseph.Kellermann@heitec.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-04Various cosmetic and coding style fixes in src/devices.Uwe Hermann
Also: - Improve a few code comments, fix typos, etc. - Change a few more variable types to u8/u16/u32 etc. - Make some very long lines fit into 80chars/line. - Drop a huge duplicated comment, use "@see" to refer to the other one. - Reduce nesting level a bit by restructuring some code chunks. - s/Config.lb/devicetree.cb/ in a few places. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27Since some people disapprove of white space cleanups mixed in regular commitsStefan Reinauer
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27Improve coreboot build output and eliminate some warnings:Uwe Hermann
- Add static and const where possible. - Turn some #warning entries into TODO comments. - Add missing prototypes. - Remove unused variables. - Fix printf arguments or cast them as needed. - Make sconfig output look better. Drop useless "PARSED THE TREE" output. - Print "(this may take a while)" while building romcc. Add missing "\n". Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watosn <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22If no pci access method has been set for the device tree so far (e.g.Carl-Daniel Hailfinger
during early coreboot_ram), pci_{read,write}_config{8,16,32} will die(). This patch changes pci_{read,write}_config{8,16,32} to use the existing PCI access method autodetection infrastructure instead of die()ing. Until r4340, any usage of pci_{read,write}_config{8,16,32} in coreboot_ram before the device tree was set up resulted in either a silent hang or a NULL pointer dereference. I changed the code in r4340 to die() properly with a loud error message. That still was not perfect, but at least it allowed people to see why their new ports died. Still, die() is not something developers like to see, and thus a patch to automatically pick a sensible default instead of dying was created. Of course, handling PCI access method selection automatically for fallback purposes has certain limitations before the device tree is set up. We only check if conf1 works and use conf2 as fallback. No further tests are done. This patch enables cleanups and readability improvements in early coreboot_ram code: Without this patch: dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x64); With this patch: dword = pci_read_config32(sm_dev, 0x64); Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21Rewrite interrupt handling in coreboot to be more comprehensible andStefan Reinauer
more flexible. Also some minore device allocator cleanups that sneaked in. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18This patch gets rid of all the implicit definition warnings for serengeti ↵Myles Watson
except get_nodes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04AMD Rev F supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-08eric patchYinghai Lu
1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-10added PCI expansion ROM support,Li-Ta Lo
works for some ATI and Nvidia AGP cards now. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-25update comment according to the new DOMLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-18- First stab at getting the ppc ports building and working.Eric Biederman
- The sandpointx3+altimus has been consolidated into one directory for now. - Added support for having different versions of the pci access functions on a per bus basis if needed. Hopefully I have not broken something inadvertently. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21- Bump the LinuxBIOS major versionEric Biederman
- Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- First pass through with with device tree enhancement merge. Most of the ↵Eric Biederman
mechanisms should be in place but don't expect anything to quite work yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-23Doxidization, reformatLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-02- Major update of the dynamic device tree so it can handleEric Biederman
* subtractive resources * merging with the static device tree * more device types than just pci - The piece to watch out for is the new enable_resources method that was needed in all of the drivers git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12- Remove all of the annoying $Id stringsEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-05-19- Cleanups on the romcc side including a pci interface that usesEric Biederman
fewer registers, and is easier to hardcode. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-24- Small step forward Linux boots and almost works...Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 02:38:07 +0000