coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-02-16	device/dram: Move SPD manufacturer names out of arch/x86	Patrick Rudolph
2020-11-16	src: Change bare 'unsigned' to 'unsigned int'	Martin Roth
2020-09-16	device/dram: Add method for converting MHz to MT/s	Rob Barnes
2020-09-14	src/include: Drop unneeded empty lines	Elyes HAOUAS
2020-07-26	src: Change BOOL CONFIG_ to CONFIG() in comments & strings	Martin Roth
2020-06-02	src: Remove redundant includes	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
2020-04-05	src/include: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2019-10-21	src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'	Elyes HAOUAS
2019-10-21	src/{drivers/vpd,include/device/dram}: Add missing 'include <stdint.h>'	Elyes HAOUAS
2019-08-14	dram: Add basic DDR4 SPD parsing	Andrey Petrov
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2018-08-21	nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.c	Patrick Rudolph
2018-08-20	nb/intel/sandybridge: Fill in DIMM serial number	Patrick Rudolph
2018-04-16	device/dram/ddr3: improve XMP support	Dan Elkouby
2018-04-09	device/dram/ddr2.c: Add methods to compute to identify dram	Arthur Heymans
2018-02-22	device/ddr2,ddr3: Rename and move a few things	Arthur Heymans
2017-12-20	device/dram/ddr2.c: Store the checksum in the decoded SPD struct	Arthur Heymans
2017-09-22	device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flag	Arthur Heymans
2017-09-06	device/dram/ddr2: Add a function to normalize tCLK	Arthur Heymans
2017-06-22	device/dram/ddr3.h: Add brackets around macro	Arthur Heymans
2017-06-16	haswell: add CBMEM_MEMINFO table when initing RAM	Matt DeVillier
2017-06-12	nb/intel/sandybridge: Improve CAS freq selection	Arthur Heymans
2017-06-09	device/dram/ddr2.c: Fix is_registered_ddr2	Arthur Heymans
2017-03-13	src/include: Fix space between type, * and variable name	Lee Leahy
2017-03-10	device/dram/ddr2: Add common ddr2 spd decoder	Patrick Rudolph
2017-03-09	src/include: Indent code using tabs	Lee Leahy
2017-03-09	src/include: Fix unsigned warnings	Lee Leahy
2016-11-20	device/dram/ddr3: Calculate CRC16 of SPD unique identifier	Kyösti Mälkki
2016-06-24	SPD: fix DDR3 SDRAM memory module types	Elyes HAOUAS
2016-06-20	include/device/dram/ddr3: Add additional frequencies	Patrick Rudolph
2016-03-05	include/device/dram: Fix DDR3-1866	Patrick Rudolph
2016-03-03	src/device/dram/ddr3: Parse additional information	Patrick Rudolph
2016-03-02	nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk	Patrick Rudolph
2016-02-20	nb/intel/sandybridge/raminit: Add XMP support	Patrick Rudolph
2016-01-18	header files: Fix guard name comments to match guard names	Martin Roth
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-07-12	Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED()	Martin Roth
2015-06-22	device: DDR3 generic code 64bit fix	Stefan Reinauer
2014-12-07	ddr3: Plumber DIMM type to parsed structure.	Vladimir Serbinenko
2014-07-29	sandy/ivybridge: Native raminit.	Vladimir Serbinenko
2013-12-17	device/dram/ddr3: Move CRC calculation in a separate function	Alexandru Gagniuc
2013-07-11	include: Fix spelling	Martin Roth
2013-06-04	DDR3: Add utilities for creating MRS commands	Alexandru Gagniuc
2013-06-03	dram: Add utilities for decoding DDR3 SPDs	Alexandru Gagniuc