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path: root/src/include/cpu
AgeCommit message (Expand)Author
2014-10-19amd: rename model_fxx_powernow to powernow.Vladimir Serbinenko
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
2014-10-17acpi_add_ssdt_pstates: Remove function.Vladimir Serbinenko
2014-08-30AMD Steppe Eagle: CPU files for new SoCBruce Griffith
2014-08-15intel/cpu: rename car.h to romstage.hAaron Durbin
2014-08-14Intel: Add common header file for CAR setupEdward O'Callaghan
2014-07-17drivers/spi: Sanitize headers from preprocessor abuseEdward O'Callaghan
2014-06-30x86 MTRR: Drop unused return valueKyösti Mälkki
2014-04-28AMD: Add common header file for CAR setupKyösti Mälkki
2014-04-16cpu/amd/agesa/family15tn: Add initial support for SMM modeAlexandru Gagniuc
2014-03-20rmodules: use rmodtool to create rmodulesAaron Durbin
2014-03-16Make POST device configurable.Idwer Vollering
2014-02-25Remove CACHE_ROM.Vladimir Serbinenko
2014-02-16x86: provide infrastructure to backup default SMM regionAaron Durbin
2014-02-11SMP: Add arch-agnostic boot_cpu()Kyösti Mälkki
2014-01-30x86: Add SMM helper functions to MP infrastructureAaron Durbin
2014-01-30x86: add SMM save state for 0x0100 revisionAaron Durbin
2014-01-30x86: parallel MP initializationAaron Durbin
2014-01-28x86: add common definitions for control registersAaron Durbin
2014-01-28x86/mtrr: don't assume size of ROM cached during CAR modeAaron Durbin
2014-01-28x86: include header to define types in useAaron Durbin
2014-01-23Multiboot: remove multiboot tables generation.Vladimir Serbinenko
2014-01-16cpu/intel: Make all Intel CPUs load microcode from CBFSAlexandru Gagniuc
2014-01-15Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki
2014-01-06cpu/cpu.h: Allow compiling with __SIMPLE_DEVICE__Vladimir Serbinenko
2013-12-26AMD boards (non-AGESA): Cleanup earlymtrr.c includesKyösti Mälkki
2013-12-21lynxpoint: Route all USB ports to XHCI in finalize stepDuncan Laurie
2013-12-13cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFSAlexandru Gagniuc
2013-12-09AMD boards: Fix includes for microcode updatesKyösti Mälkki
2013-11-24smi: Update mainboard_smi_gpi() to have 32bit argumentDuncan Laurie
2013-10-13Rename cpu/x86/car.h to arch/early_variables.hStefan Reinauer
2013-09-21CBMEM: Always select CAR_MIGRATIONKyösti Mälkki
2013-08-15Include boot_cpu.c for romstage buildsKyösti Mälkki
2013-08-05AMD Kabini: Add CPU AGESA wrapper for new AMD processor familySiyuan Wang
2013-07-11include: Fix spellingMartin Roth
2013-06-03include/cpu/amd: Align `CPU_ID_EXT_FEATURES_MSR` with other definesPaul Menzel
2013-05-25Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`Ronald G. Minnich
2013-05-16x86: add cache-as-ram migration optionAaron Durbin
2013-05-11Make early x86 POST codes written to IO port optionalMartin Roth
2013-05-10Get rid of a number of __GNUC__ checksStefan Reinauer
2013-05-10Drop prototype guarding for romccStefan Reinauer
2013-05-08x86: use asmlinkage macro for smm_handler_tAaron Durbin
2013-05-07x86: add TSC_CONSTANT_RATE optionAaron Durbin
2013-05-01x86: use boot state callbacks to disable rom cacheAaron Durbin
2013-04-12Revert "siemens/sitemp_g1p1: Make ACPI report the right mmconf region"Nico Huber
2013-04-10siemens/sitemp_g1p1: Make ACPI report the right mmconf regionPatrick Georgi
2013-04-05mtrr: add rom caching comment about hyperthreadsAaron Durbin
2013-04-04AMD: Drop six copies of wrmsr_amd and rdmsr_amdKyösti Mälkki
2013-04-03intel/microcode.h: Fix typo in comment: micr*o*codePaul Menzel
2013-04-01boot: add disable_cache_rom() functionAaron Durbin
2013-03-29x86: add rom cache variable MTRR index to tablesAaron Durbin
2013-03-29x86: mtrr: add CONFIG_CACHE_ROM supportAaron Durbin
2013-03-29x86: add new mtrr implementationAaron Durbin
2013-03-22x86: unify amd and non-amd MTRR routinesAaron Durbin
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
2013-03-21x86: protect against abi assumptions from compilerAaron Durbin
2013-03-19intel microcode: split up microcode loading stagesAaron Durbin
2013-03-15Google Link: Add remaining code to support native graphicsRonald G. Minnich
2013-03-15haswell: reserve default SMRAM spaceAaron Durbin
2013-03-14x86: SMM Module SupportAaron Durbin
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2013-02-27smm: Update rev 0x30101 SMM revision save stateAaron Durbin
2013-02-18AMD Family12h: Fix warningsMartin Roth
2013-02-11Intel: Replace MSR 0xcd with MSR_FSB_FREQPatrick Georgi
2013-02-09speedstep: Deduplicate some MSR identifiersPatrick Georgi
2012-12-06Unify assembler function handlingStefan Reinauer
2012-11-20Unify use of bool config variablesStefan Reinauer
2012-11-14SMM: Avoid use of global variables in SMI handlerDuncan Laurie
2012-11-13Pass the CPU index as a parameter to startup.Ronald G. Minnich
2012-11-12Fix gcc-4.7 building problem.Han Shen
2012-11-05Overhaul speedstep codeNico Huber
2012-11-01Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber
2012-09-05buildsystem: Make CPU microcode updating more configurableAlexandru Gagniuc
2012-08-09AMD northbridge: copy TOP_MEM and TOP_MEM2 for distributionKyösti Mälkki
2012-08-09Synchronize rdtsc instructionsStefan Reinauer
2012-08-07Move cpus_ready_for_init() to AMD K8Kyösti Mälkki
2012-07-31Revert "Use broadcast SIPI to startup siblings"Sven Schnelle
2012-07-25SMM: rename tseg_fixup to tseg_relocate and exportDuncan Laurie
2012-07-24SMM: Fix state save map for sandybridge and TSEGDuncan Laurie
2012-07-24Add code to read Intel microcode from CBFSVadim Bendebury
2012-07-04Intel cpus: Extend cache to cover complete Flash DeviceKyösti Mälkki
2012-07-03AGESA F15 wrapper for Trinityzbao
2012-07-02Use broadcast SIPI to startup siblingsSven Schnelle
2012-07-02Intel CPUs: execute microcode update only once per coreKyösti Mälkki
2012-05-24cbtypes.h: Unify cbtypes.h used in AMD board's codeVikram Narayanan
2012-05-08Clean up #ifsPatrick Georgi
2012-04-27SMM: unify mainboard APM command handlersStefan Reinauer
2012-04-27cpu/cpu.h: add ROMCC guardsStefan Reinauer
2012-04-26Revamp Intel microcode update codeStefan Reinauer
2012-04-25Replace cache control magic numbers with symbolsPatrick Georgi
2012-04-06Fixes and Sandybridge support for lapic cpu initStefan Reinauer
2012-04-04Add support to run SMM handler in TSEG instead of ASEGStefan Reinauer
2012-04-03Add support for Intel Turbo Boost featureStefan Reinauer
2012-03-30Make MTRR min hole alignment 64MBDuncan Laurie
2012-03-30Add an option to keep the ROM cached after romstageStefan Reinauer
2012-03-29Add infrastructure for global data in the CAR phase of bootGabe Black
2012-03-16xchg is atomic with side-effectsPatrick Georgi
2012-03-08Unify Local APIC address definitionsPatrick Georgi
2012-02-16AGESA F15: AGESA family15 model 00-0fh cpu wrapperKerry Sheh
2012-01-10MTRR: get physical address size from CPUIDSven Schnelle
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