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2009-04-06(trivial) fix some warningsStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13This, ladies and gentlement, is commit #4000.Stefan Reinauer
Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few include files and missing prototypes. Also, fix up the Config-abuild.lb files to properly work for cross compiling. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06* fix a minor power state issue in the ich7 smm handlerStefan Reinauer
* move mainboard dependent code into a mainboard SMI handler. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-01Some changes required to get yabel working on v2 (and they generally makeStefan Reinauer
sense, too). Have one u64 instead of three. In order to use the old bios emulator, you have to do nothing. (Default, if CONFIG_PCI_ROM_RUN is enabled) In order to use yabel in your target, you need to add the following lines to your config: uses CONFIG_PCI_OPTION_ROM_RUN_YABEL default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1 In order to use vm86 in your target, you need to add the following lines to your config: uses CONFIG_PCI_OPTION_ROM_RUN_VM86 default CONFIG_PCI_OPTION_ROM_RUN_VM86=1 Note: vm86 only works on platforms with _RAMBASE in the lower megabyte. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-14Change Log:Rudolf Marek
Bellongs to r3947 Following patch adds dynamically generated P-States infrastructure as well as M2V-MX SE as example how to do that. It is based on AMD code and mine code for ACPI generation. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20fix compiler warnings (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11[PATCH] coreboot-v2: Add multiboot supportRobert Millan
Signed-off-by: Robert Millan <rmh@aybabtu.com> Acked-by: Jordan Crouse <jordan@cosmicpneguin.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Support for the Intel ICH7 southbridge.Stefan Reinauer
This includes an early SMI handler. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02Go back to SIPI WAIT state for those CPUS defining the newly introducedStefan Reinauer
CONFIG_AP_IN_SIPI_WAIT flag. Newer Intel CPUs need this to operate with multiple cores. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer
code is changed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19Changed the stop_this_cpu() to just hlt.Marc Jones
Removed local APIC INIT (don't worry the APIC and AP are still initialized). The local APIC INIT seemed to be the incorrect thing to do to stop an AP. The Intel Multiprocessor specification indicated that a vector should be set and a START should happen following an INIT. Then AP will execute the instructions pointed to by the vector. There is no vector or start in stop_this_cpu(). This seems to put the AP in an in-between state. In the case of Barcelona the AP's MSRs and PCI register are not accessible by the hardware debugger. The better solution seems to be to just put the AP in a hlt and allow the AP to go into C1. Then APIC managing software running on the BSP can program the AP as needed. Signed-off-by: Marc Jones <marc.jones@amd.com> Reviewed-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19Initial AMD Barcelona support for rev Bx.Marc Jones
These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization. Signed-off-by: Marc Jones <marc.jones@amd.com> Reviewed-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <myles@pel.cs.byu.edu> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10This patch cleans up and clarifies Geode source code comments.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This repairs the other Geode mainboards so they'll build with the newMarc Jones
Geode changes. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This patch adds support for the AMD Geode LX CPU. (rediffed)Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-03Add missing license headers to some Geode LX related files.Jordan Crouse
The following original authors agreed to the license: - Ronald G. Minnich <rminnich@gmail.com> - Indrek Kruusa <indrek.kruusa@artecdesign.ee> - Stefan Reinauer <stepan@coresystems.de> - Andrei Birjukov <andrei.birjukov@artecdesign.ee> Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06two more directories from YhLu's mcp55 megapatch.Yinghai Lu
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com> Signed-off-by: Ed Swierk <eswierk at arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward at gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-01This fixes a small typo.Roman Kononov
Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support inYinghai Lu
serengeti_cheeatah git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04amdk8_sysconfYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04AMD Rev F supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13changes for the lx and artecgroup moboIndrek Kruusa
Signed-off-by: Indrek Kruusa Approved-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-25- USB P4 as host fixRichard Smith
This should make the USB P4 work as a USB host git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-25- Added suport for enabling USB P4 on the olpcRichard Smith
USB P4 is disabled by default and we need to setup the mux bits proper to make it work. This is the frame work for that. All thats needed is the right address values git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-03Changelog:Indrek Kruusa
* src/cpu/amd/model_lx/model_lx_init.c L2 cache initialization removed (moved to northbridge.c) * src/include/cpu/amd/lxdef.h more checked values * src/northbridge/amd/lx/northbridge.c L2 cache initialization added cpubug() commented out * src/northbridge/amd/lx/raminit.c empty function sdram_set_registers() is in use, don't remove * src/mainboard/artecgroup/dbe61/Config.lb irqmap changes * src/mainboard/artecgroup/dbe61/irq_tables.c tentative changes to irq table (currently not in use) * src/mainboard/artecgroup/dbe61/mainboard.c irq assigned manually to NIC * src/mainboard/artecgroup/dbe61/Options.lb gcc 4.0 is OK * targets/artecgroup/dbe61/Config.lb 64K for VSA is OK at moment Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-02Geode LX: this patch adds configuration/status/self-test MSR definitionsIndrek Kruusa
for L2 cache and fixes wrong P2D defines. This also patch adds L2 cache initialization for Geode LX CPU. Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-28This patch adds support for the AMD LX cpu. Ron Minnich
There is one global change to pci_ids.h. The rest are changes for LX. I ran abuild and it is ok. Not all artec design changes are included as some of them would adversely affect other mainboards. Indrek will need to test. Signed-off-by: Ron Minnich Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec design. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-21These changes incorporate steve goodrich'es fixes, and one bug that isRonald G. Minnich
disabled. cs5536: add new entires for SB control etc. cs5536.c: chip_enabled function moved to chip_init, so it only gets run once. IRQ setup improved gx2def.h: new defines added vr.h: new file, with new def's for virtual register control. mainboard config.lb: new entries added for nb and sb control. chipsetinit.c: new controls added -- I forget all the details :-) grphinit.c: new function added northbridge.c: new IRQ control added. FlashChipSetup added, controlled by chip info setupflash struct member. Currently, if enabled, this hangs OLPC in linux PCI scan. chip.h: new struct members added for unwanted device enable, flash setup git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-10changes from AMD for making OLPC video work.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-04mods for early printing on OLPCRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-02Fall back to pre-broken settings and setup for GX2. Ronald G. Minnich
We lost a few things, but this is still worth it. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-27code cleanup, comments addedLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-10added chipsetinit function, many defines. addec call to chipsetinit to Ronald G. Minnich
northbridge.c builds fine on lippert git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-10add cpureginit to romcc code.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-10clean up gx2def.h a bit. Ronald G. Minnich
Add cpureginit.c added called to cpureginit to model_gx2_init.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-06add northbridgeinit, also add new constants.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-06fix constants styleRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-06add bug support for 2.1Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-03new cache_as_ram support Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-20fix conflichRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-20resolve conflictLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-20added definitions. added cpubug support. added object. Commented out Ronald G. Minnich
msr set in northbridge that conflicted with the cpubug support. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-20add a defineRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-13correct __ROMCC__Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-13failed attempt to do early init for cs5535. Almost there butLi-Ta Lo
still get garbage reading smbus. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-02-27more GX2 commitLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-02-06add this fileRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-021201_ht_bus0_dev0_fidvid_core.diffStefan Reinauer
https://openbios.org/roundup/linuxbios/issue41 Lord have mercy upon us. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-01Applying YhLu's patch from issue 37.Stefan Reinauer
a. apic id liftting to way that kernel like and let bsp to stay with 0 b. hw memhole: solve if hole_startk == some node basek This, together with the previous one will break most of the tree, but Yinghai Lu is really good at fixing things, so... git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-23added missing microcode.hLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-25- See Issue Tracker id-4 "lnxi-patch-4" Jason Schildt
- In addition: modified apic_id lifting to always lift all CPUs. This may cause problems with older kernels. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12added include file for sc520Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-08-10Undoing all HDAMA commits from LNXI from r2005->2003Jason Schildt
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-08-09- Merge from linuxbios-lnxi (Linux Networx repository) up to public tree.Jason Schildt
- Special version for HDAMA rev G with 33Mhz test and reboot out. - Support for CPU rev E, dual core, memory hoisting, - corrected an SST flashing problem. Kernel bug work around (NUMA) - added a Kernel bug work around for assigning CPU's to memory. r2@gog: svnadmin | 2005-08-03 08:47:54 -0600 Create local LNXI branch r1110@gog: jschildt | 2005-08-09 10:35:51 -0600 - Merge from Tom Zimmerman's additions to the hdama code for dual core and 33Mhz fix. r1111@gog: jschildt | 2005-08-09 11:07:11 -0600 Stable Release tag for HDAMA-1.1.8.10 and HDAMA-1.1.8.10LANL r1112@gog: jschildt | 2005-08-09 15:09:32 -0600 - temporarily removing hdama tag to update to public repository. Will reset tag after update. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-08eric patchYinghai Lu
1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-34arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-29arch import user (historical)
Creator: Hamish Guthrie <hamish@prodigi.ch> Added NSC pc97317 super-io and added fill character option to config/Options.lb to speed up flash programming git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-18- First stab at getting the ppc ports building and working.Eric Biederman
- The sandpointx3+altimus has been consolidated into one directory for now. - Added support for having different versions of the pci access functions on a per bus basis if needed. Hopefully I have not broken something inadvertently. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-12ooops. sorryStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-11fix a little more of ppcStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- First stab at running linuxbios without the old static device tree.Eric Biederman
Things are close but not quite there yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- remove old cpu header filesEric Biederman
- Update cpu.h for the new cpu initialization scheme git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- Renamed cpu header filesEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-06epia-m supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-22fixed to follow linuxbios usage.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-11- Moved hlt() to it's own header.Eric Biederman
- Reworked pnp superio device support. Now complete superio support is less than 100 lines. - Added support for hard coding resource assignments in Config.lb - Minor bug fixes to romcc - Initial support for catching the x86 processor BIST error codes. I've only seen this trigger once in production during a very suspcious reset but... - added raminit_test to test the code paths in raminit.c for the Opteron - Removed the IORESOURCE_SET bit and added IORESOURCE_ASSIGNED and IORESOURCE_STORED so we can tell what we have really done. - Added generic AGP/IOMMU setting code to x86 - Added an implementation of memmove and removed reserved identifiers from memcpy - Added minimal support for booting on pre b3 stepping K8 cores - Moved the checksum on amd8111 boards because our default location was on top of extended RTC registers - On the Hdama added support for enabling i2c hub so we can get at the temperature sensors. Not that i2c bus was implemented well enough to make that useful. - Redid the Opteron port so we should only need one reset and most of memory initialization is done in cpu_fixup. This is much, much faster. - Attempted to make the VGA IO region assigment work. The code seems to work now... - Redid the error handling in amdk8/raminit.c to distinguish between a bad value and a smbus error, and moved memory clearing out to cpufixup. - Removed CONFIG_KEYBOARD as it was useless. See pc87360/superio.c for how to setup a legacy keyboard properly. - Reworked the register values for standard hardware, moving the defintions from chip.h into the headers of the initialization routines. This is much saner and is actually implemented. - Made the hdama port an under clockers BIOS. I debuged so many interesting problems. - On amd8111_lpc added setup of architectural/legacy hardware - Enabled PCI error reporting as much as possible. - Enhanded build_opt_tbl to generate a header of the cmos option locations so that romcc compiled code can query the cmos options. - In romcc gracefully handle function names that degenerate into function pointers - Bumped the version to 1.1.6 as we are getting closer to 2.0 TODO finish optimizing the HT links of non dual boards TODO make all Opteron board work again TODO convert all superio devices to use the new helpers TODO convert the via/epia to freebios2 conventions TODO cpu fixup/setup by cpu type git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-11 - O2, enums, and switch statements work in romccEric Biederman
- Support for compiling romcc on non x86 platforms - new romc options -msse and -mmmx for specifying extra registers to use - Bug fixes to device the device disable/enable framework and an amd8111 implementation - Move the link specification to the chip specification instead of the path - Allow specifying devices with internal bridges. - Initial via epia support - Opteron errata fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-01- Remove useless definitionsEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21- First pass at s2880 support.Eric Biederman
- SMP cleanups (remove SMP only use CONFIG_SMP) - Minor tweaks to romcc to keep it from taking forever compiling - failover fixes - Get a good implementation of k8_cpufixup and sizeram for the opteron git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-19- Major cleanup of the bootpathEric Biederman
- Changes to allow more code to be compiled both ways - Working SMP support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-17- Minor mod to reset16.inc to work with newer binutils hopefully this works ↵Eric Biederman
with older ones... - Update apic.h to include the APIC_TASK_PRI register definition - Update mptable.c to have a reasonable board OEM and productid - Additional testfiles for romcc. - Split out auto.c and early failover.c moving their generic bits elsewere - Enable cache of the rom - Fixes to amd8111_lpc.c so that we successfully setup virtual wire mode on the ioapic git-svn-id: svn://svn.coreboot.org/coreboot/trunk@880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-13More FB2 stuffGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-22- Initial checkin of the freebios2 treeEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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