Age | Commit message (Expand) | Author |
2014-04-28 | AMD: Add common header file for CAR setup | Kyösti Mälkki |
2014-04-16 | cpu/amd/agesa/family15tn: Add initial support for SMM mode | Alexandru Gagniuc |
2014-03-20 | rmodules: use rmodtool to create rmodules | Aaron Durbin |
2014-03-16 | Make POST device configurable. | Idwer Vollering |
2014-02-25 | Remove CACHE_ROM. | Vladimir Serbinenko |
2014-02-16 | x86: provide infrastructure to backup default SMM region | Aaron Durbin |
2014-02-11 | SMP: Add arch-agnostic boot_cpu() | Kyösti Mälkki |
2014-01-30 | x86: Add SMM helper functions to MP infrastructure | Aaron Durbin |
2014-01-30 | x86: add SMM save state for 0x0100 revision | Aaron Durbin |
2014-01-30 | x86: parallel MP initialization | Aaron Durbin |
2014-01-28 | x86: add common definitions for control registers | Aaron Durbin |
2014-01-28 | x86/mtrr: don't assume size of ROM cached during CAR mode | Aaron Durbin |
2014-01-28 | x86: include header to define types in use | Aaron Durbin |
2014-01-23 | Multiboot: remove multiboot tables generation. | Vladimir Serbinenko |
2014-01-16 | cpu/intel: Make all Intel CPUs load microcode from CBFS | Alexandru Gagniuc |
2014-01-15 | Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR | Kyösti Mälkki |
2014-01-06 | cpu/cpu.h: Allow compiling with __SIMPLE_DEVICE__ | Vladimir Serbinenko |
2013-12-26 | AMD boards (non-AGESA): Cleanup earlymtrr.c includes | Kyösti Mälkki |
2013-12-21 | lynxpoint: Route all USB ports to XHCI in finalize step | Duncan Laurie |
2013-12-13 | cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS | Alexandru Gagniuc |
2013-12-09 | AMD boards: Fix includes for microcode updates | Kyösti Mälkki |
2013-11-24 | smi: Update mainboard_smi_gpi() to have 32bit argument | Duncan Laurie |
2013-10-13 | Rename cpu/x86/car.h to arch/early_variables.h | Stefan Reinauer |
2013-09-21 | CBMEM: Always select CAR_MIGRATION | Kyösti Mälkki |
2013-08-15 | Include boot_cpu.c for romstage builds | Kyösti Mälkki |
2013-08-05 | AMD Kabini: Add CPU AGESA wrapper for new AMD processor family | Siyuan Wang |
2013-07-11 | include: Fix spelling | Martin Roth |
2013-06-03 | include/cpu/amd: Align `CPU_ID_EXT_FEATURES_MSR` with other defines | Paul Menzel |
2013-05-25 | Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h` | Ronald G. Minnich |
2013-05-16 | x86: add cache-as-ram migration option | Aaron Durbin |
2013-05-11 | Make early x86 POST codes written to IO port optional | Martin Roth |
2013-05-10 | Get rid of a number of __GNUC__ checks | Stefan Reinauer |
2013-05-10 | Drop prototype guarding for romcc | Stefan Reinauer |
2013-05-08 | x86: use asmlinkage macro for smm_handler_t | Aaron Durbin |
2013-05-07 | x86: add TSC_CONSTANT_RATE option | Aaron Durbin |
2013-05-01 | x86: use boot state callbacks to disable rom cache | Aaron Durbin |
2013-04-12 | Revert "siemens/sitemp_g1p1: Make ACPI report the right mmconf region" | Nico Huber |
2013-04-10 | siemens/sitemp_g1p1: Make ACPI report the right mmconf region | Patrick Georgi |
2013-04-05 | mtrr: add rom caching comment about hyperthreads | Aaron Durbin |
2013-04-04 | AMD: Drop six copies of wrmsr_amd and rdmsr_amd | Kyösti Mälkki |
2013-04-03 | intel/microcode.h: Fix typo in comment: micr*o*code | Paul Menzel |
2013-04-01 | boot: add disable_cache_rom() function | Aaron Durbin |
2013-03-29 | x86: add rom cache variable MTRR index to tables | Aaron Durbin |
2013-03-29 | x86: mtrr: add CONFIG_CACHE_ROM support | Aaron Durbin |
2013-03-29 | x86: add new mtrr implementation | Aaron Durbin |
2013-03-22 | x86: unify amd and non-amd MTRR routines | Aaron Durbin |
2013-03-22 | x86: Unify arch/io.h and arch/romcc_io.h | Stefan Reinauer |
2013-03-21 | x86: protect against abi assumptions from compiler | Aaron Durbin |
2013-03-19 | intel microcode: split up microcode loading stages | Aaron Durbin |
2013-03-15 | Google Link: Add remaining code to support native graphics | Ronald G. Minnich |
2013-03-15 | haswell: reserve default SMRAM space | Aaron Durbin |
2013-03-14 | x86: SMM Module Support | Aaron Durbin |
2013-03-01 | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel |
2013-02-27 | smm: Update rev 0x30101 SMM revision save state | Aaron Durbin |
2013-02-18 | AMD Family12h: Fix warnings | Martin Roth |
2013-02-11 | Intel: Replace MSR 0xcd with MSR_FSB_FREQ | Patrick Georgi |
2013-02-09 | speedstep: Deduplicate some MSR identifiers | Patrick Georgi |
2012-12-06 | Unify assembler function handling | Stefan Reinauer |
2012-11-20 | Unify use of bool config variables | Stefan Reinauer |
2012-11-14 | SMM: Avoid use of global variables in SMI handler | Duncan Laurie |
2012-11-13 | Pass the CPU index as a parameter to startup. | Ronald G. Minnich |
2012-11-12 | Fix gcc-4.7 building problem. | Han Shen |
2012-11-05 | Overhaul speedstep code | Nico Huber |
2012-11-01 | Merge cpu/intel/acpi.h into cpu/intel/speedstep.h | Nico Huber |
2012-09-05 | buildsystem: Make CPU microcode updating more configurable | Alexandru Gagniuc |
2012-08-09 | AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution | Kyösti Mälkki |
2012-08-09 | Synchronize rdtsc instructions | Stefan Reinauer |
2012-08-07 | Move cpus_ready_for_init() to AMD K8 | Kyösti Mälkki |
2012-07-31 | Revert "Use broadcast SIPI to startup siblings" | Sven Schnelle |
2012-07-25 | SMM: rename tseg_fixup to tseg_relocate and export | Duncan Laurie |
2012-07-24 | SMM: Fix state save map for sandybridge and TSEG | Duncan Laurie |
2012-07-24 | Add code to read Intel microcode from CBFS | Vadim Bendebury |
2012-07-04 | Intel cpus: Extend cache to cover complete Flash Device | Kyösti Mälkki |
2012-07-03 | AGESA F15 wrapper for Trinity | zbao |
2012-07-02 | Use broadcast SIPI to startup siblings | Sven Schnelle |
2012-07-02 | Intel CPUs: execute microcode update only once per core | Kyösti Mälkki |
2012-05-24 | cbtypes.h: Unify cbtypes.h used in AMD board's code | Vikram Narayanan |
2012-05-08 | Clean up #ifs | Patrick Georgi |
2012-04-27 | SMM: unify mainboard APM command handlers | Stefan Reinauer |
2012-04-27 | cpu/cpu.h: add ROMCC guards | Stefan Reinauer |
2012-04-26 | Revamp Intel microcode update code | Stefan Reinauer |
2012-04-25 | Replace cache control magic numbers with symbols | Patrick Georgi |
2012-04-06 | Fixes and Sandybridge support for lapic cpu init | Stefan Reinauer |
2012-04-04 | Add support to run SMM handler in TSEG instead of ASEG | Stefan Reinauer |
2012-04-03 | Add support for Intel Turbo Boost feature | Stefan Reinauer |
2012-03-30 | Make MTRR min hole alignment 64MB | Duncan Laurie |
2012-03-30 | Add an option to keep the ROM cached after romstage | Stefan Reinauer |
2012-03-29 | Add infrastructure for global data in the CAR phase of boot | Gabe Black |
2012-03-16 | xchg is atomic with side-effects | Patrick Georgi |
2012-03-08 | Unify Local APIC address definitions | Patrick Georgi |
2012-02-16 | AGESA F15: AGESA family15 model 00-0fh cpu wrapper | Kerry Sheh |
2012-01-10 | MTRR: get physical address size from CPUID | Sven Schnelle |
2011-11-01 | remove trailing whitespace | Stefan Reinauer |
2011-11-01 | Remove XIP_ROM_BASE | Patrick Georgi |
2011-10-28 | Get rid of AUTO_XIP_ROM_BASE | Patrick Georgi |
2011-09-15 | Build warning fix for AMD Family 12 | efdesign98 |
2011-09-12 | Miscellaneous AMD F14 warning fixes | efdesign98 |
2011-08-04 | cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. | Keith Hui |
2011-07-13 | Make AMD SMM SMP aware | Rudolf Marek |
2011-06-28 | Addition of Family12/SB900 wrapper code | efdesign98 |