| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2005-07-08 | eric patch | Yinghai Lu | |
| 1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 | |||
| 2005-07-06 | Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51 | arch import user (historical) | |
| Creator: Yinghai Lu <yhlu@tyan.com> cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 | |||
| 2004-10-14 | - Renamed cpu header files | Eric Biederman | |
| git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 | |||
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index : coreboot.git | |
| my copy of coreboot | User & |
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