Age | Commit message (Expand) | Author |
2020-07-26 | src/include: Add missing includes | Elyes HAOUAS |
2020-06-16 | sb,soc/intel: Replace smm_southbridge_enable_smi() | Kyösti Mälkki |
2020-06-16 | soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS) | Kyösti Mälkki |
2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
2020-05-06 | treewide: replace GPLv2 long form headers with SPDX header | Patrick Georgi |
2020-05-06 | treewide: Move "is part of the coreboot project" line in its own comment | Patrick Georgi |
2020-04-05 | src/include: Use SPDX for GPL-2.0-only files | Angel Pons |
2020-03-17 | src (minus soc and mainboard): Remove copyright notices | Patrick Georgi |
2020-03-15 | treewide: Replace uses of "Nehalem" | Angel Pons |
2019-11-22 | cpu/intel/smm: Drop em64t save state | Arthur Heymans |
2019-11-22 | intel/smm: Provide common smm_relocation_params | Kyösti Mälkki |
2019-11-04 | cpu/intel/em64t101: Add Nehalem to compatibility list | Arthur Heymans |
2019-10-01 | cpu/intel/common: Move intel_ht_sibling() to common folder | Patrick Rudolph |
2019-09-19 | cpu/x86/lapic: Refactor timer_fsb() | Kyösti Mälkki |
2019-08-28 | intel/smm/gen1: Use smm_subregion() | Kyösti Mälkki |
2019-08-26 | soc/intel: Use common romstage code | Kyösti Mälkki |
2019-08-22 | arch/x86: Add <arch/romstage.h> | Kyösti Mälkki |
2019-08-18 | cpu/intel: Enter romstage without BIST | Kyösti Mälkki |
2019-08-15 | intel/smm: Define struct ied_header just once | Kyösti Mälkki |
2019-08-15 | soc/intel: Rename some SMM support functions | Kyösti Mälkki |
2019-08-15 | intel/smm/gen1: Rename header file | Kyösti Mälkki |
2019-08-15 | cpu/intel: Refactor platform_enter_postcar() | Kyösti Mälkki |
2019-08-13 | cpu/x86: Separate save_state struct headers | Kyösti Mälkki |
2019-01-27 | src/cpu/intel: Set get_ia32_fsb function common | Elyes HAOUAS |
2019-01-08 | cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK | Kyösti Mälkki |
2018-12-30 | cpu/intel/car: Drop remains of setup_stack_and_mtrrs() | Kyösti Mälkki |
2018-12-28 | soc/intel: Drop romstage_after_car() | Kyösti Mälkki |
2018-12-18 | Fix typos involving "the the" | Jonathan Neuschäfer |
2018-10-22 | intel: Use CF9 reset (part 2) | Patrick Rudolph |
2018-10-11 | src: Move common IA-32 MSRs to <cpu/x86/msr.h> | Elyes HAOUAS |
2018-10-05 | src: Fix MSR_PKG_CST_CONFIG_CONTROL register name | Elyes HAOUAS |
2018-07-30 | cpu/intel/microcode: Add helper functions to get microcode info | Rizwan Qureshi |
2018-06-02 | cpu/intel/car: Prepare for some POSTCAR_STAGE support | Kyösti Mälkki |
2017-12-11 | intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c | Elyes HAOUAS |
2017-11-30 | intel: Replace msr(0x198) with msr(IA32_PERF_STATUS) | Elyes HAOUAS |
2017-09-08 | soc/intel/common/block: Common ACPI | Shaunak Saha |
2017-05-16 | cpu/intel/turbo: Add option to disable turbo | Subrata Banik |
2017-03-13 | src/include: Wrap lines at 80 columns | Lee Leahy |
2017-03-13 | src/include: Move storage class to beginning of declaration | Lee Leahy |
2017-03-13 | src/include: Fix space between type, * and variable name | Lee Leahy |
2016-11-11 | intel post-car: Separate files for setup_stack_and_mtrrs() | Kyösti Mälkki |
2016-11-09 | cpu/intel: Add MSR to support enabling turbo frequency | Shaunak Saha |
2016-11-02 | soc/intel/apollolake: Disable Monitor and Mwait feature | Venkateswarlu Vinjamuri |
2016-06-22 | intel: Drop old romstage main() without asmlinkage | Kyösti Mälkki |
2016-06-18 | intel: Fix romstage main() with asmlinkage | Kyösti Mälkki |
2016-02-10 | cpu/intel/microcode: allow microcode to be loaded in romstage | Aaron Durbin |
2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
2015-07-29 | Add SoC specific microcode update check in ramstage | Rizwan Qureshi |
2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
2015-02-16 | acpi: Generate valid ACPI processor objects | Timothy Pearson |
2014-08-15 | intel/cpu: rename car.h to romstage.h | Aaron Durbin |
2014-08-14 | Intel: Add common header file for CAR setup | Edward O'Callaghan |
2014-01-16 | cpu/intel: Make all Intel CPUs load microcode from CBFS | Alexandru Gagniuc |
2013-12-13 | cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS | Alexandru Gagniuc |
2013-05-10 | Drop prototype guarding for romcc | Stefan Reinauer |
2013-04-03 | intel/microcode.h: Fix typo in comment: micr*o*code | Paul Menzel |
2013-03-19 | intel microcode: split up microcode loading stages | Aaron Durbin |
2013-02-11 | Intel: Replace MSR 0xcd with MSR_FSB_FREQ | Patrick Georgi |
2013-02-09 | speedstep: Deduplicate some MSR identifiers | Patrick Georgi |
2012-11-05 | Overhaul speedstep code | Nico Huber |
2012-11-01 | Merge cpu/intel/acpi.h into cpu/intel/speedstep.h | Nico Huber |
2012-09-05 | buildsystem: Make CPU microcode updating more configurable | Alexandru Gagniuc |
2012-07-24 | Add code to read Intel microcode from CBFS | Vadim Bendebury |
2012-07-02 | Intel CPUs: execute microcode update only once per core | Kyösti Mälkki |
2012-04-26 | Revamp Intel microcode update code | Stefan Reinauer |
2012-04-06 | Fixes and Sandybridge support for lapic cpu init | Stefan Reinauer |
2012-04-03 | Add support for Intel Turbo Boost feature | Stefan Reinauer |
2011-08-04 | cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. | Keith Hui |
2010-12-11 | factor out cpu power management base into a separate file. And fix a bug in | Stefan Reinauer |
2010-11-18 | For completeness sake: License header. | Patrick Georgi |
2010-11-17 | Move Intel power management related defines to some central location. | Patrick Georgi |
2009-01-20 | fix compiler warnings (trivial) | Stefan Reinauer |
2004-10-14 | - Renamed cpu header files | Eric Biederman |