summaryrefslogtreecommitdiff
path: root/src/include/cpu/intel
AgeCommit message (Expand)Author
2018-10-05src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS
2018-07-30cpu/intel/microcode: Add helper functions to get microcode infoRizwan Qureshi
2018-06-02cpu/intel/car: Prepare for some POSTCAR_STAGE supportKyösti Mälkki
2017-12-11intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2cElyes HAOUAS
2017-11-30intel: Replace msr(0x198) with msr(IA32_PERF_STATUS)Elyes HAOUAS
2017-09-08soc/intel/common/block: Common ACPIShaunak Saha
2017-05-16cpu/intel/turbo: Add option to disable turboSubrata Banik
2017-03-13src/include: Wrap lines at 80 columnsLee Leahy
2017-03-13src/include: Move storage class to beginning of declarationLee Leahy
2017-03-13src/include: Fix space between type, * and variable nameLee Leahy
2016-11-11intel post-car: Separate files for setup_stack_and_mtrrs()Kyösti Mälkki
2016-11-09cpu/intel: Add MSR to support enabling turbo frequencyShaunak Saha
2016-11-02soc/intel/apollolake: Disable Monitor and Mwait featureVenkateswarlu Vinjamuri
2016-06-22intel: Drop old romstage main() without asmlinkageKyösti Mälkki
2016-06-18intel: Fix romstage main() with asmlinkageKyösti Mälkki
2016-02-10cpu/intel/microcode: allow microcode to be loaded in romstageAaron Durbin
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-07-29Add SoC specific microcode update check in ramstageRizwan Qureshi
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
2014-08-15intel/cpu: rename car.h to romstage.hAaron Durbin
2014-08-14Intel: Add common header file for CAR setupEdward O'Callaghan
2014-01-16cpu/intel: Make all Intel CPUs load microcode from CBFSAlexandru Gagniuc
2013-12-13cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFSAlexandru Gagniuc
2013-05-10Drop prototype guarding for romccStefan Reinauer
2013-04-03intel/microcode.h: Fix typo in comment: micr*o*codePaul Menzel
2013-03-19intel microcode: split up microcode loading stagesAaron Durbin
2013-02-11Intel: Replace MSR 0xcd with MSR_FSB_FREQPatrick Georgi
2013-02-09speedstep: Deduplicate some MSR identifiersPatrick Georgi
2012-11-05Overhaul speedstep codeNico Huber
2012-11-01Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber
2012-09-05buildsystem: Make CPU microcode updating more configurableAlexandru Gagniuc
2012-07-24Add code to read Intel microcode from CBFSVadim Bendebury
2012-07-02Intel CPUs: execute microcode update only once per coreKyösti Mälkki
2012-04-26Revamp Intel microcode update codeStefan Reinauer
2012-04-06Fixes and Sandybridge support for lapic cpu initStefan Reinauer
2012-04-03Add support for Intel Turbo Boost featureStefan Reinauer
2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
2010-12-11factor out cpu power management base into a separate file. And fix a bug inStefan Reinauer
2010-11-18For completeness sake: License header.Patrick Georgi
2010-11-17Move Intel power management related defines to some central location.Patrick Georgi
2009-01-20fix compiler warnings (trivial)Stefan Reinauer
2004-10-14- Renamed cpu header filesEric Biederman
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 06:07:41 +0000