| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-12-11 | intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c | Elyes HAOUAS |
| 2017-11-30 | intel: Replace msr(0x198) with msr(IA32_PERF_STATUS) | Elyes HAOUAS |
| 2016-11-09 | cpu/intel: Add MSR to support enabling turbo frequency | Shaunak Saha |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-02-16 | acpi: Generate valid ACPI processor objects | Timothy Pearson |
| 2013-05-10 | Drop prototype guarding for romcc | Stefan Reinauer |
| 2013-02-11 | Intel: Replace MSR 0xcd with MSR_FSB_FREQ | Patrick Georgi |
| 2013-02-09 | speedstep: Deduplicate some MSR identifiers | Patrick Georgi |
| 2012-11-05 | Overhaul speedstep code | Nico Huber |
| 2012-11-01 | Merge cpu/intel/acpi.h into cpu/intel/speedstep.h | Nico Huber |
| 2012-04-06 | Fixes and Sandybridge support for lapic cpu init | Stefan Reinauer |
| 2010-12-11 | factor out cpu power management base into a separate file. And fix a bug in | Stefan Reinauer |
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index : coreboot.git | |
| my copy of coreboot | User & |
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