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2023-05-16ec/google/chromeec: Use host command APICaveh Jalali
Update the chromeec driver to use the EC host command API. Large blocks of repetitive code to set up EC calls are replaced with single function calls to perform the same operation. BUG=b:258126464 BRANCH=none TEST=booted on rex Change-Id: I0317405b1ed0c58568078133c17c8cfbc7c21d80 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73325 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-16ec/google/chromeec: Add ec_cmd_api.h, update ec_commands.hCaveh Jalali
The new util/chromeos/update_ec_headers.sh utility is used to update ec_commands.h and introduce ec_cmd_api.h from the chrome EC repo. ec_cmd_api.h is a new file from the chrome EC repo which defines the API for communicating with the EC. It is a companion to the existing ec_commands.h by defining functions corresponding to EC host command opcodes and request/response struct definitions. See $EC/docs/ec-host-command-api.md for details. Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: 3e35858003 ec: Add another #line directive The original include/ec_cmd_api.h version in the EC repo is: 59de61f2db zephyr: Add support for RNG devices BUG=b:258126464 BRANCH=none TEST=none Change-Id: I30f20e34d31b7e19cf03f65fefd58ae64eef1d41 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73324 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13ec/quanta/ene_kb3940q/acpi: Fix PS2K under WindowsMatt DeVillier
Add _HID to parent SIO device so Windows can find the PS2K, and remove _ADR since HID and ADR are mutually exclusive. TEST=build/boot Win11 on google/butterfly, verify keyboard functional. Change-Id: I772ceef1b439cfd4e2740e53362bee9d494fb36d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-07ec/google/chromeec: Handle ACPI S4 in chromeec_smi_sleep()Kyösti Mälkki
While Chromebook hardware originally would not have the capacity to do suspend-to-disk (ACPI S4), the power management code in EC should react to S4 request as if it was S5 request. Change-Id: Ida9118919c8149d94f470847d0c4aad9c0b97d3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03ec/starlabs/merlin: Change the fallback value for fn_ctrl_swapSean Rhodes
Change the fallback value of the `fn_ctrl_swap` option to 0, which is disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I76329ec59ba630c987a122bffb8045150facdf08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-04-28ec/starlabs/merlin: Change the fallback value for fn_ctrl_swapSean Rhodes
Change the fallback value of the `fn_ctrl_swap` option to 0, which is disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9fcbb497f14ed0c97ff05c6c01a3929522786781 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-28ec/starlabs/merlin/acpi: Don't attempt to change EC valuesSean Rhodes
The EC will constantly update the battery variables approximately every 60 seconds; they should be used unmodified, rather than trying to change them. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3cff0ac6a322018cbca33b5f90dd62b3475da25c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-14ec/acpi/ec: replace misleading "recv_ec_data_timeout" console outputFelix Held
In the non-timeout case in recv_ec_data_timeout, a message like this one will get printed at BIOS_SPEW log level: "recv_ec_data_timeout: 0x00". The "timeout" part of the function name corresponds to what the function does, but the message will only be printed when not running into the timeout which is a bit misleading and might suggest a problem when there is none. To avoid this possible confusion, don't use the function name in the printk, but use "Data from EC:" instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I521f67517f64fc64e24853d96730c3f9459f1ccc Reviewed-on: https://review.coreboot.org/c/coreboot/+/74381 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-12Reland "drivers/intel/dptf: Add multiple fan support under dptf"Sumeet Pawnikar
This reverts commit 4dba71fd25c91a9e610287c61238a8fe24452e4e. Add multiple fan support for dptf policies. This also fixes the Google Meet resolution drop issue as per b:246535768 comment#12. When system starts Google Meet video call, it uses the hardware accelerated encoder as expected. But, as soon as another system connects to the call, an immediate fallback is observed from hardware to software encoder. Due to this, Google Meet resolution dropped from 720p to 180p. This issue is observed on Alder Lake-N SoC based fanless platforms. This same issue was not seen on fan based systems. With the fix in dptf driver where fan configures appropriate setting for only fan participant, not for other device participants, able to see consistent 720p resolution. BUG=b:246535768,b:235254828 BRANCH=None TEST=Built and tested on Alder Lake-P Redrix system for two fans support and on Alder Lake-N fanless systems. With this code change Google Meet resolution drop not observed. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: Id07d279ff962253c22be9d395ed7be0d732aeaa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73249 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12ec/google/chromeec: Use either EC or MB lid switch stateKarthikeyan Ramasubramanian
With CB:16732, EC can provide default lid switch implementation(LID0 ACPI device). Up until that point, mainboard has been providing default switch implementation. When EC provides lid switch implementation, the lid switch state is read from EC either through MMAP or LPC interface. Hence there is no need to keep mainboard's LIDS ACPI object in sync with EC's lid switch state. Use only EC's lid switch state on boards using EC's implementation. This paves the way to remove LIDS ACPI object on those mainboards. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Trigger lid open/close events and ensure that they are detected properly through /proc/acpi/button/lid/LID0/state. localhost ~ # cat /proc/acpi/button/lid/LID0/state state: open localhost ~ # cat /proc/acpi/button/lid/LID0/state state: closed Ensure that the system behaves as expected based on powerd configuration. After signin, system suspends/resumes for lid close/open. On signin screen, system shuts down/boots for lid close/open. Change-Id: I013574d7c21761f167ad38aeed27a419677b8000 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-08ec/lenovo/pmh7/chip.h: Use 'bool' instead of 'int'Elyes Haouas
This to fix following error using Clang-16.0.0: /cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:135:22: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .backlight_enable = 0x01, ^~~~ /cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:136:23: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .dock_event_enable = 0x01, ^~~~ Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-04ec/starlabs/merlin: Add support for the ITE mirror flagSean Rhodes
When enabled, the EC will mirror the firmware contained inside the coreboot ROM. This allows it to be updated at the same time as coreboot. Enable the mirror flag if the installed EC firmware does not match the target version or if a CMOS option, "manual_mirror_flag" is set. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I377abbb37dc4d3e535e518a73e73969b25967daa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-09Revert "ec/starlabs/merlin: Add support for enabling the mirror flag"Sean Rhodes
This reverts commit b42ca4d0b2fafe7214396d30a1a833ac33cf85bc. Reason for revert: The mirror flag "0x01" is mirror once, which relies on the EC remembering that it's been mirrored. However, the EC forgets this if it's been without power for 20 minutes or so. Even if power is connected then, it'll instantly try to mirror and it can't charge whilst doing it. It can either result in incomplete EC firmware, or a loop where it's constantly trying to mirror. Change-Id: I79da9143cc63459e7e29431eff2cb14200424b37 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-04{ec,mb}/system76: Move smbios_system_wakeup_typeTim Crawford
Move the implementation of smbios_system_wakeup_type from the mainboards to the EC for all models that use System76 EC (everything except KBL). Change-Id: Iaace234ca87e8a05eaa006a438d2c9eb13ce4d76 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-02acpi/ec: Handle new host event EC_HOST_EVENT_BODY_DETECT_CHANGETim Van Patten
Handle the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE. Previously, the EC sent the host event EC_HOST_EVENT_MODE_CHANGE when body detection changed between lap/desk mode. However, that event is a wake event, which resulted in spurious AP wake events being triggered when the EC detected lap/desk mode changes while the AP was suspended. To resolve this, the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE was added, which will not be a wake event. This CL adds handling for the new event to acpi/ec.asl to switch DPTC tables when a change is detected. BRANCH=none BUG=b:261141172 TEST=bodydetectmode on|off, verify host event is received Change-Id: Iabeb7891489a209f45504804355f1fa817082976 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73298 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-02-27ec/google/chromeec: Update ec_commands.hTim Van Patten
Update ec_commands.h from the EC repo at: "8441cf4 Add host event: EC_HOST_EVENT_BODY_DETECT_CHANGE" This is an exact copy of the EC repo's ec_commands.h with the exception of updating the copyright message. BUG=b:261141172 BRANCH=none TEST=built coreboot for skyrim Change-Id: I9892c0c3518f63d357459861e8fa1b7f5f494e68 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73258 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2023-02-19treewide: Remove useless "_STA: Status" commentElyes Haouas
Change-Id: I99ded00fa6dadb494c1523d00063dbc1fde95614 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73093 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-17treewide: Remove unuseful "_UID: Unique ID" commentElyes Haouas
Change-Id: I150a4ed94bcaead6eb45f1c4b4952ae6957e0940 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_HID: Hardware ID" commentElyes Haouas
Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-08ec/dell: Add support for the SMSC MEC5035Nicholas Chin
This is required to prevent the EC from shutting down the system after about 15 seconds after being turned on. If the EC doesn't receive a command meaning "CPU OK" it assumes that the processor has failed and flashes a diagnostic code on the keyboard LEDs to indicate this. This also enables the keyboard and trackpad/trackpoint interfaces. Parts of this code were derived from yet-to-be merged code in CB:44975 (ec: Add support for MEC5055 for Dell laptops) written by Iru Cai. Tested on a Dell Latitude E6400 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Change-Id: Ia420cd51e9a64be5eee4af2c0d113618575522b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59703 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08ec/google/chromeec: Update ec_commands.hCaveh Jalali
Update ec_commands.h from the EC repo at: "8b6f7de2a7 fan: update fan stalled value reporting" This is an exact copy of the EC repo's ec_commands.h with the exception of updating the copyright message. BUG=b:258110734 BRANCH=none TEST=built coreboot for brya Change-Id: I4ce15e1af40cc54a6cf2ebd6f5d5adf8953dee60 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-08ec/google/chromeec: clang-format ec_commands.hCaveh Jalali
This is a format-only change: Reformat ec_commands.h using clang-format according to the EC repo's current formatting style. The command is: clang-format --style=file:$EC/.clang-format -i ec_commands.h where $EC points to the chromeos EC repo. The EC repo has recently adpoted the practice of formatting all files through clang-format using its own style. So, run ec_commands.h through the EC's clang-format so future updates don't get overwhelmed by inconsequential style changes. BUG=b:258110734 BRANCH=none TEST=built coreboot for brya Change-Id: Icbd6d00922dc5fd4c44ee109d54cea612e15db06 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-01ec/google/wilco/acpi: Add DPTF RCDP() methodMatt DeVillier
The Windows DPTF drivers expect this method, and if not present appear to hang. Adding this method fixes DPTF under Windows on drallion. Modeled after existing method used by chrome-ec. TEST=build/boot Win11 on google/drallion, verify DPTF functional. Change-Id: I6570345379da413273251ecf5209c4997aac9b11 Original-patch-by: Coolstar <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2023-01-28ec/google/chrome-ec: Demote Vivaldi printk from error to infoMatt DeVillier
Not all Chrome-EC devices have a keyboard or use Vivaldi for key remapping, so demote the printk output when the EC doesn't support it from ERROR to INFO. Adjust the printk text for clarity. Change-Id: I14059f4e3e56ff891f302601d5acc1bb842cffc1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72474 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22ec/google/chromeec/acpi/ec: add scope comment to nested #endifFelix Held
To make the code slightly easier to read, add a comment about the scope to the #endif of the outer #ifdef block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic2bc83c77750cd8a509f4755fdfa4daaf082d754 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2023-01-11ec/google/chromeec: Add retimer flag for mux devicePrashant Malani
Not all ports have retimers. Add a property to denote that a particular port has a retimer (instead of assuming that all ports have retimers). BUG=b:263964979 TEST=Verified on guybrush; SSDT shows retimer-switch on port1 when device tree is updated accordingly. Change-Id: I754323236d2912777b63cede0fce2ccf7882cfea Signed-off-by: Prashant Malani <pmalani@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71663 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10chromeos/cr50_enable_update.c: Clear EC AP_IDLE flagDerek Huang
When AP boots up after Cr50 firmware update and reboot, AP finds that Cr50 reset is required for Cr50 to pick the new firmware so it trigger Cr50 reset and power off the system, AP expects system will power on automatically after Cr50 reset. However this is not the case for Chromebox, Chromebox EC set AP_IDLE flag when system is shutting down, when AP_IDLE flag is set in EC, the system stays at S5/G3 and wait for power button presssend. It cause an issue in factory that the operator needs to press power button to power on the DUT after Cr50 firmware update. This patch sends EC command to direct EC to clear AP_IDLE flag after AP shutdown so AP can boot up when Cr50 reset. BUG=b:261119366 BRANCH=firmware-brya-14505.B TEST=DUT boots up after Cr50 firmware update in factory test flow Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-29{ec,mb}/system76/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ia5ae30a1ee976b8059936027b28ac56f37279217 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71516 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{superio,ec}/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I449ec5b0bbf3f24d51688efef151d3018d2848b2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71524 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{superio,ec}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I5c77b6d1e1dc1134f62dcb3e93df01dc9c2f386c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71520 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26tree/acpi: Replace Divide(a,b,c,d) with ASL 2.0 syntaxFelix Singer
Replace `Divide (a, b, c, d)` with these instructions: c = a % b d = a / b Change-Id: I44366be5b5145a5d19f85df7a2f338866cb9c8b0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-26tree/acpi: Replace Not(a) with ASL 2.0 syntaxFelix Singer
Replace `Not (a)` with `~a`. Change-Id: I53993fb7b46b3614d18ee001323f17efacbf04c1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace And(a,b) with ASL 2.0 syntaxFelix Singer
Replace `And (a, b)` with `a & b`. Change-Id: Id8bbd1a477e6286bbcb5fa31afd1c7a860b1c7dc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70851 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace And(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `And (a, b, c)` with `c = a & b`, respectively `c &= b` where possible. Change-Id: Ie558f9d0b597c56ca3b31498edb68de8877d3a2f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70850 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace Or(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Or (a, b, c)` with `c = a | b`, respectively `c |= b` where possible. Change-Id: Icf194b248075f290de90fb4bc4e9a0cd9d76ec61 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70846 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace ShiftLeft(a,b) with ASL 2.0 syntaxFelix Singer
Replace `ShiftLeft (a, b)` with `a << b`. Change-Id: I812b1ed9dcf3a5749b39a9beb9f870258ad6a0de Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70842 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace ShiftLeft(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `ShiftLeft (a, b, c)` with `c = a << b`. Change-Id: Ibd25a05f49f79e80592482a1b0532334f727af58 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70841 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace ShiftRight(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `ShiftRight (a, b, c)` with `c = a >> b`. One case was simplified to just `a >> b`. Change-Id: I889012b0a3067138e6f02d3fe8e97151effb5c2a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70840 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-19tree: Replace Or(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Or (a, b)` with `a | b`. Change-Id: I73842cd4843ebb0b48440059ae9dcf6c82235a76 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70845 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19tree: Replace XOr(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `XOr (a, b, c)` with `c = a ^ b`, respectively `c ^= b` where possible. Change-Id: Ic5f67684bbd4ea115c4dae8a4417d88bea0d6b77 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70843 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19ec/starlabs/merlin: Add EC related files for Cezanne laptopsSean Rhodes
Add EC memory layout and Q events for AMD Cezanne based boards, the "StarBook Mk VI" and "StarFighter Mk I", which both use the ITE 5570E. Change-Id: I87806b830b3d58a6ce3b89f45b5a07f4502a87f3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68333 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16ec/kontron/it8516e/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I16890206d517f0455d29c1642cbbe642a3312481 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70679 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-15treewide: Remove unused 'include <arch/io.h>'Elyes Haouas
Change-Id: I6f1d7625eb457084ba893b25518fdfdb59cf64db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-14ec/smsc/mec1308/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I0a419c861e84cd96e8337957dc62a7ca5b981e14 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14ec/quanta/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I00a6ece73048209861221cba5f2c7381adfa54b9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14ec/google/chromeec/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I2cdb1c9ae3a33bfc72767ff60d8948054d4e151a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14ec/lenovo/h8/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I1c68816f47aa3ed0ab3bf55d4cfde71d5838d051 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12ec/lenovo/h8/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLessEqual (a, b)` with `a <= b`. Change-Id: I76855f9d4564fc08cd70456e2a0b1514cd73e35f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70620 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12ec/clevo/it5570e/acpi: Replace Index(a, b) with ASL 2.0 syntaxFelix Singer
Replace `Index (FOO, 1337)` with `FOO[1337]`. Change-Id: If035eac6b6eb06f79eb6596364bc41069ba42f70 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12ec/purism/librem-ec/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ie29511ad0b8e24feb478152009d7f4e8ed3ad26d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2022-12-09mb/intel/mtlrvp: Add MTL-P RVP board idsJamie Ryu
This adds MTL-P board id definition. Change include, 1. Add board_id.c implementation 2. Add board_id.h implementation 3. Add board_id config in variants.h 4. Makefile changes BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I90b0543d5db208f696d2c2c2dc3d2581514a845b Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66102 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-06src/ec/intel: Create common code for board_id implementationHarsha B R
This patch creates initial common code structure for board_id implementation for intel rvp platforms. Board_id helps in identifying the platform with respect to CHROME_EC and INTEL_EC (Windows_EC). Changes include 1. Create initial board_id.c and board_id.h 2. Modify the Makefile to include src/ec/intel directory BUG=b:260654043 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: If133f6a72b8c3e1d8811a11f91e4556beb8c16e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-01vboot: Allow for comparison of hash without zero-paddingJakub Czapiga
Adjust asserts to allow to store and compare (at S3 resume) hashes without padding to maximum hash length / slot size. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: If6d46e0b58dbca86af56221b7ff2606ab2d1799a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-01ec/google/chromec: Add DPTC support for host event 1/2/9EricKY Cheng
DTTS is Dynamic Thermal Table Switching Proposal. Add DPTC support for host event lid-open/lid-close/Thermal Threshold. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I156a9d138ccac7f75cc0dd0d827f7a721fcbc782 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67793 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-30ec/google/chromeec: Add packed attribute to structs in unionArthur Heymans
Clang warns about structs inside a union also needing the packed attribute. This files is copied from the chromeec project, so it adds comment next to the coreboot specific changes as a reference. TEST: google/vilboz remains the same with BUILD_TIMELESS=1 and gcc. Change-Id: I8b5233618081db86caedcb2d14870974e109ed9b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-22ec: Add SPDX license headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie5355e05982b372ef69515cfa081e2afbc7b09fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/68981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17{ec/superio}/acpi: Remove _PRS if no _SRS is implementedArthur Heymans
_PRS only makes sense if _SRS is implemented. Change-Id: I030bd716215b5ac5738e00ebf6ed991d9d6c5ca0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-12ec/google/chromeec: Deprecate dev_index from google_chromeec_rebootCaveh Jalali
This removes the dev_index argument from the google_chromeec_reboot API. It's always set to 0, so don't bother passing it. BUG=b:258126464 BRANCH=none TEST=none Change-Id: Iadc3d7c6c1e048e4b1ab8f8cec3cb8eb8db38e6a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69373 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12ec/google/chromeec: Simplify error handling for GET_VERSIONCaveh Jalali
We don't need to check the lower level error code to determine if an EC call succeeded. Simply check the return value of the call. BUG=b:258126464 BRANCH=none TEST=none Change-Id: Iaf0795b0c1a2df0d3f44e6098ad02b82e33c5710 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69372 Reviewed-by: Boris Mittelberg <bmbm@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-12ec/google/chromeec: Simplify get_uptime_info error handlingCaveh Jalali
google_chromeec_get_uptime_info() doesn't need to return an error code from the lower level calls for the caller to interpret. It is more appropriate to return a success/failure boolean. BUG=b:258126464 BRANCH=none TEST=none Change-Id: I3e27b8b4eed9d23e6330eda863e43ca78bb174a3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69371 Reviewed-by: Boris Mittelberg <bmbm@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-11ec/clevo/it5570e: add driver for EC used on various Clevo laptopsMichael Niewöhner
This adds a driver for the ITE IT5570E EC in combination with Clevo vendor EC firmware. The interface is mostly identical on various laptop models. Thus, we have implemented one common driver to support them all. The following features were implemented: - Basics like battery, ac, etc. - Suspend/hibernate support: S0ix, S3*, S4/S5 - Save/restore of keyboard backlight level during S0ix without the need for Clevo vendor software (ControlCenter) - Flexicharger - Fn keys (backlight, volume, airplane etc.) - Various configuration options via Kconfig / CMOS options * Note: S3 support works at least on L140CU (Cometlake), but it's not enabled for this board because S0ix is used. Not implemented, yet: - Type-C UCSI: the EC firmware seems to be buggy (with vendor fw, too) - dGPU support is WIP An example of how this driver can be hooked up by a board can be seen in in change CB:59850, where support for the L140MU is added. Known issues: - Touchpad toggle: The touchpad toggle (Fn-F1) has two modes, Ctrl-Alt-F9 mode and keycodes 0xf7/0xf8 mode. Ctrl-Alt-F9 is the native touchpad toggle shortcut on Windows. On Linux this would switch to virtual console 9, if enabled. Thus, one should use the keycodes mode and add udev rules as specified in [1]. If VT9 is disabled, Ctrl-Alt-F9 mode could be used to set up a keyboard shortcut command toggling the touchpad. - Multi-fan systems The Clevo NV41MZ (w/o dGPU) has two fans that should be in-sync. However, the second fan does not spin. This needs further investigation. [1] https://docs.dasharo.com/variants/clevo_nv41/post_install/ Testing the various functionalities of this EC driver was done in the changes hooking up this driver for the boards. Change-Id: Ic8c0bee9002ad9edcd10c83b775fc723744caaa0 Co-authored-by: Michał Kopeć <michal.kopec@3mdeb.com> Co-authored-by: Michał Żygowski <michal.zygowski@3mdeb.com> Co-authored-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-11ec/starlabs/merlin: Rename the Cezanne EC codeSean Rhodes
This EC code is for the Byte, a Cezanne Mini PC. The EC is different to the Cezanne StarBook Mk VI. Rename it to `-desktop`, so the laptop variant becomes the primary. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I25f812cb1c6cefca1ebbe3bee5d20cf521dd60af Reviewed-on: https://review.coreboot.org/c/coreboot/+/68319 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10ec/google/chromeec: Fix USB_PD_PORTS response data typeCaveh Jalali
The EC_CMD_USB_PD_PORTS host command returns a struct ec_response_usb_pd_ports, not a struct ec_response_charge_port_count. Luckily, both structs have the same memory layout, so this is simply a name change. BUG=b:258126464 BRANCH=none TEST=none Change-Id: I0d7710ca8a45f0ea3939f58bbba6bab31ff41919 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69370 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10ec/google/chromeec: Simplify KEYBOARD_BACKLIGHT error handlingCaveh Jalali
Simplify the implementation of setting the keyboard backlight PWM value. Host command stubs typcially don't need to examine the host command's return value as stored in cmd_code because that level of detail is not very interesting. Higher value error codes are returned in actual result structures. This host command can return EC_RES_ERROR for out of range PWM values which is already a generic error and unlikely to happen since we already limit the range to 0..100 here. Finally, none of the callers in coreboot check the return value. BUG=b:258126464 BRANCH=none TEST=none Change-Id: If17bc4e31baba02ba2f7ae8e7a5cbec7f97688c5 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69369 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10ec/google/chromeec: Fix keyboard_backlight callCaveh Jalali
The EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT command does not return data, so don't specify a result buffer. BUG=b:258126464 BRANCH=none TEST=none Change-Id: I5b9a0d228e187a9337498246a3b9ed8db07b95c7 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2022-11-10google/chromeec: Add ACPI method for EC PanicRob Barnes
Add an ACPI method to handle EC_HOST_EVENT_PANIC (bit 24) events. EC panic is not covered by the standard (0-F) ACPI notify values. Arbitrarily choosing B0 notify, which is in the 84-BF device specific ACPI notify range. This will be a no-op until the kernel driver is also updated to handle this event. BUG=b:258195448 BRANCH=None TEST=Observe event with modified cros_ec_lpc driver Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Iafa642c1c50f9a0083a8e618e1eabec9a7ce39b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69391 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09ec/google/chromec: Expand EC share memory for DTTSEricKY Cheng
DTTS is Dynamic Thermal Table Switching Proposal. DTTS needs one bit to save the body detection result from EC. Define mode change STTB bit for Desktop (1) and laptop (0). This bit is Switch thermal table by body detection status. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07ec/starlabs/merlin: Add support for enabling the mirror flagSean Rhodes
When enabled, the EC will mirror the firmware contained inside the coreboot ROM. This allows it to be updated at the same time as coreboot. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ief088e012b65be32648f581fc3190e1000bca241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-03ec/google/wilco: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: I93f02674fde0415e4d831ec13541a806bbc3bd91 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-10-25ec/google/wilco/superio: Fix PS2K under WindowsMatt DeVillier
PS2K device needs to be under PCI0, not LPCB, for Windows to recognize it. Same change was made to ChromeEC previously. Test: Boot Win11 on Drallion, verify built-in keyboard functional. Change-Id: I12019592dfa1d869ba57c1ff6c25ac6bdeb7a300 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-20Revert "drivers/intel/dptf: Add multiple fan support under dptf"Sumeet Pawnikar
This reverts commit 672bd9bee5c0045694ef20fe3e2f7a003bef0edd. Reason for revert: Gmeet resolution dropped. When system starts Gmeet video call, it uses the hardware accelerated encoder as per the expectation. But, as soon as another system connects to the call, the immediate fallback observed from hardware to software encoder. Due to this, Gmeet resolution dropped from 720p to 180p. Currently, this issue observed on AlderLake-N SoC based fanless platforms. This issue is not seen on fan based systems. BUG=b:246535768,b:235254828 BRANCH=None TEST=Built and tested on Alderlake-N systems. With this revert Gmeet resolution drop not observed. Change-Id: Idaeaeaed47be44166a7cba9a0a1fac50d2688e50 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2022-10-20ec/google/wilco/acpi: Hide CrOS-specific devices from OSMatt DeVillier
Set _STA to 0xB for GOOG000C/GOOG000E devices to prevent showing as missing drivers under Windows. Change-Id: I0887fd6e18528d2c8523e7bc66db9efaa31adf5d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68462 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14ec/google/chromeec: Demote LPC EC error printk from ERR to SPEWMatt DeVillier
Several EC host commands check for support of a given feature or msg version, and a non-zero response does not necessarily indicate an actual error. Since the caller is (should be) handling the non-zero response to the host command, demote the EC printk from ERR to SPEW to clean up the console log and prevent non-errors from causing false failures in firmware tests. BUG=b:238961053 Change-Id: Ib7afc0b7e5b571acb56252f7adb518a6b2716b62 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68259 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07ec/starlabs/merlin: Add EC related files for Alder Lake boardsSean Rhodes
Add EC memory layout and Q events for Intel Alder Lake based boards, the "StarBook Mk VI" and "StarFighter Mk I", which both use the ITE 5570E. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8cea386ba91d076084002738fe7041834deea311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06ec/starlabs/merlin: Add support for enabling fast chargeSean Rhodes
The Lite Mk IV's can enable fast charging, with support up to 100W via USB-C PD 3.0. The default for this is disabled, as it can reduce battery life span. This patch adds the option to enable fast charging, by writing 0x01 to 0x18 in the EC space. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie01eb59d3f41b242190973fd9c58b1494320c12a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-05ec/lenovo/h8/acpi: Fix wrongly used operatorFelix Singer
Commit 37a89d519d4e ("ec/lenovo/h8/acpi: Replace Not() with ASL 2.0 syntax") mixed up boolean and bit-wise operators while replacing Not() with ASL 2.0 syntax. Thus, fix that. Built dsdt.aml of lenovo/x230 and differs, but it remains the same when this commit is applied after commit 37a89d519d4e. Change-Id: Ifa848aafb5480acaac4fabffcf90a3dbf5248e43 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66380 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-27ec/lenovo/h8: Add Kconfig option for Fn-Ctrl swapAngel Pons
Having to use a runtime configurable option backend like CMOS just to specify the value of the "fn_ctrl_swap" option is annoying. Introduce a new Kconfig option to allow specifying the fallback value, which is only used when the option backend cannot provide a value. Change-Id: I00bb3cd60c443fc0c8adb82e8e0c436dfc5de24b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67836 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14timer: Change timer util functions to 64-bitRob Barnes
Since mono_time is now 64-bit, the utility functions interfacing with mono_time should also be 64-bit so precision isn't lost. Fixed build errors related to printing the now int64_t result of stopwatch_duration_[m|u]secs in various places. BUG=b:237082996 BRANCH=All TEST=Boot dewatt Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-05ec/google/chromeec: Modify ufp from type-c roleDtrain Hsu
In order to fix the USB port of type-C dongle has no function after reboot/shutdown, modify ufp which is in google_chromeec_usb_pd_get_info from the bit1 of type-c role (PD_CTRL_RESP_ROLE_DATA). BUG=b:239138412 TEST=Built coreboot image and verified that using this patch can detect usb drive after reboot. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I73a4a6ec37129388783599125f067068d155d93f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67168 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04drivers/intel/dptf: Add multiple fan support under dptfSumeet Pawnikar
Add multiple fan support for dptf policies BUG=b:235254828 BRANCH=None TEST=Built and tested on Redrix system for two fans Change-Id: I96ead90e3b805bd20de03e4bef4fa4b9fbaaaedd Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-31acpi: Replace EC_ENABLE_AMD_DPTC_SUPPORT with Kconfig valueTim Van Patten
Compile-time support of DPTC is controlled by EC_ENABLE_AMD_DPTC_SUPPORT in each variant's ec.h file. This CL removes EC_ENABLE_AMD_DPTC_SUPPORT and replaces it with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. Each variant's run-time support of DPTC continues to be controlled by the variant's overridetree.cb "dptc_enable" value. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ic101e74bab88e20be0cb5aaf66e4349baa1432e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-26ec/google/chromeec: Call PNOT() when Battery Status ChangesTim Van Patten
PNOT() should be called when the battery status changes, to give the SOC an opportunity to handle it. This is in preparation for the low/no battery boot changes. This CL also updates the PNOT() comments to better match the name of the function and why it's called. BRANCH=none BUG=b:217911928 TEST=Boot skyrim Change-Id: I8b74313d242fd4959315a67579eb6c5f49a31a76 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66993 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-26ec/starlabs/merlin/cml: Correct the offset for Max ChargeSean Rhodes
The offset for Max Charge is located at 0x1a, so correct this in the definitions and EC memory ACPI. Change-Id: I92cc452d1189e62db78aed787f2de65fd5096564 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-24ec/google/chromeec/acpi: Add support for DPTF oem variable event notifyTony Huang
The agah EC code will monitor adapter current to choose corresponding DPTF oem variable table. When it changes, this event will send to the ACPI FW through host event and then pass onto the DPTF kernel driver. This patch adds support for that feature. BUG=b:238921409 TEST=add Printf() calls to the ACPI, and check these Printf() will show up in the kernel log when EC send oem variable table change notify. Change-Id: I1dbbfd9b3d65b56d77050c9ba9957e54530c3a0e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66574 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18ec/google: Notify DPTF driver power participant on PD eventVarshit B Pandya
The DPTF power participant device needs to be notified when power source changes so it can re-evaluate power source and power source change count, this can be later used by DPTF along with methods provided by EC. Corresponding changes in EC are https://crrev.com/c/3545778 and https://crrev.com/c/3547317 BUG=b:205928013 TEST=Build, boot brya0 and dump DSDT to check change Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I07f58b928a0dba92bec3817177142c586e5014b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-17ec/google/chromec: Add BFIV, BFCTTim Van Patten
The flag EC_BATT_FLAG_CUT_OFF was added with the CL: 3704470: battery: Set battery cutoff flag https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3704470 This flag is set in the ACPI memory mapped area when the command `ectool batterycutoff` is issued so ACPI code can respond appriopriately. This CL adds the flags to coreboot ACPI. BRANCH=none BUG=b:217911928 TEST=Boot nipperkin with low & no battery TEST=Boot skyrim with low & no battery Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I4e63ff4fc2d6b0ecf767a6bffd81f823c74c15bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/66803 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-16ec/system76/ec: Provide charging thresholds by defaultTim Crawford
Battery charging thresholds are a firmware implementation and not dependent on any hardware. It is expected that all boards using System76 EC firmware will select this option, so enable it by default. Leave it disabled on clevo/cml-u, which didn't have it selected. Change-Id: Id99d36eaf055a76b9e1eb732174017651de299a5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-14commonlib: Substitude macro "__unused" in compiler.hBill XIE
Since there are many identifiers whose name contain "__unused" in headers of musl libc, introducing a macro which expands "__unused" to the source of a util may have disastrous effect during its compiling under a musl-based platform. However, it is hard to detect musl at build time as musl is notorious for having explicitly been refusing to add a macro like "__MUSL__" to announce its own presence. Using __always_unused and __maybe_unused for everything may be a good idea. This is how it works in the Linux kernel, so that would at least make us match some other standard rather than doing our own thing (especially since the other compiler.h shorthand macros are also inspired by Linux). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-13ec/google/chromec: Update ACPI handlers for GPUTim Wawrzynczak
There is a new field in EC EMEM for arbitrary GPU data to be passed from EC to ACPI FW; this patch adds support for it. Also the current host event for _Q0C (EC_HOST_EVENT_USB_CHARGER) is unused, and is being repurposed in the next CL, so this patch drops the handler. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iff6f935a5bdc8c47277eaa6bcbedd5fc5ed311a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65485 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-09ec/system76/ec: Hide ACPI device S76DJeremy Soller
Hide the device so that Windows does not warn about a missing driver. Tested on system76/lemp10: - EC functionality remains functional on Linux 5.18.6 and Windows 10. - Windows 10 does not report the device in Device Manager. Change-Id: Iffcb873b85e077535d4de5806d01ba309f46c017 Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64700 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-04treewide: Unify Google brandingJon Murphy
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-30ec/google/chromeec: Update ec_commands.hYu-Ping Wu
This change copies ec_commands.h directly from the ChromiumOS EC repo, with the exception of changing the copyright header to SDPX format. Update to commit SHA1 2cbf6fbf (ec_commands: Drop VBNV read/write support). BUG=b:178689388 TEST=none BRANCH=none Change-Id: I74fa8b1171ca109dee163a7657659cdac1687450 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65469 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-24ec/google/chromeec: Remove google_chromeec_vbnv_context()Yu-Ping Wu
With CB:65012, google_chromeec_vbnv_context() is no longer used. Remove it from the codebase. BUG=b:178689388 TEST=./util/abuild/abuild -t GOOGLE_STOUT -a -x Change-Id: I717f600f0f73c3ca932b6a442a9d5b90c35c8f3b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-24device/resource: Modify some resource allocation instancesKyösti Mälkki
These changes made my crude pattern matching work with coccinelle simpler. Change-Id: I83f3ef38b8663640594b4d726838f7a6f96a58a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-24ec/acpi: Return error codes on timeoutAbel Briggs
The `send` and `recv` API functions currently print error messages if a timeout occurs while polling the EC, but they perform the I/O transaction regardless. This can put the EC in a bad state or otherwise invoke undefined hardware behavior. Most callers ignore the return value currently, but for callers which do not, we should make sure our behavior is correct. Signed-off-by: Abel Briggs <abelbriggs1@hotmail.com> Change-Id: Ifb87dd1ac869807fd08463bd8fef36d0389b325e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64350 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22ec/lenovo/pmh7: Add IORESOURCE_ASSIGNED flagKyösti Mälkki
This makes coccinelle script happy, everyone else sets flags last. Change-Id: I80f421aeacb6e72fea2265c69cafb2a0d89e5616 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-22ec/kontron/kempld: Fix IORESOURCE_IRQKyösti Mälkki
The IRQ was incorrecly allocated as IO resource. It's not possible for new_resource() to return NULL. Change-Id: I66811b36b44f06cb39df8e9cdab87be0e2ef8eb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-06-15ec/google/chromeec: Add property to denote mux mode switchPrashant Malani
On some systems, the Chrome EC controls both the USB Type-C mux as well as the retimer. Introduce a boolean property "mode-switch" to denote switches which act as a mode-switch. BUG=b:235834631 TEST=None BRANCH=None Signed-off-by: Prashant Malani <pmalani@chromium.org> Change-Id: If209a8529ff7ec424f23fd96875ac95a1fe6267d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-10ec/google/chromeec: Add support to report fan speed via ACPISumeet Pawnikar
Add fan speed rpm control for DPTF based Active2 policy as per document #626708, by utilizing existing FAN0 variable from src/ec/google/chromeec/acpi/emem.asl#18. There is no corresponding EC change required for this policy support because EC fan code already exporting this rpm value using EC_MEMMAP_FAN for FAN0. BUG=b:224457192 BRANCH=None TEST=Built and booted on ADL-P based Brya system and verify the fan speed in rpm under sysfs path cat /sys/bus/acpi/devices/INTC1048\:00/fan_speed_rpm. Change-Id: Ibb1646b1fb1659fd853ece97d97bb9dee2a3f57e Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-09ec/lenovo/h8/acpi: Replace Not() with ASL 2.0 syntaxFelix Singer
Change-Id: I8a0f18d37c065827a0f5b54f24ea1fcde497c504 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>