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Replace `Add (a, b)` with `a + b`.
Change-Id: Ie1c21437a0d97ff1039775adcb915547fac71bf5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Add (a, b)` with `a + b`.
Change-Id: I5ed8c8a8cfc92b0af1602bee15cd6971536b61ad
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Add (a, b)` with `a + b`.
Change-Id: I82a960f9b5748ccdde3c07b78963b44b8dbef37e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Subtract (a, b)` with `a - b`.
Change-Id: Ia736b0080848e029eaeae094f1d2cc12aace3730
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Subtract (a, b)` with `a - b`.
Change-Id: Ibdc3faa5c888b1bd0e5234ed8185dcf29b2f1d4d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Subtract (a, b)` with `a - b`.
Change-Id: Id8fec71cc174008f48fc0a80c36942e6941982ac
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Subtract (a, b)` with `a - b`.
Change-Id: Ib47fdb28c2047e001902345ad2f1b25fe5d8a152
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Add (a, b, c)` with `c = a + b`.
Change-Id: I4f8b71c90f0c56fdb29c4d2e9a2a737f704f3265
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Add (a, b, c)` with `c = a + b`.
Change-Id: Ibbc0831e688b62d7ed0dec5e4b7224688ed0ae6d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Add (a, b, c)` with `c = a + b`.
Change-Id: I48d471730d36200f5496effaad00a06222be85d9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Add (a, b, c)` with `c = a + b`.
Change-Id: Iaa79ea4bdb4a33fd2445ae9033c740dacc090037
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Subtract (a, b, c)` with `c = a - b`.
Change-Id: Ifcdc29dbc3874180bd0692260ea250a1a6c86d41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Subtract (a, b, c)` with `c = a - b`.
Change-Id: Ic38c60503fedaffc66153e103d40fda86781f9c8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Subtract (a, b, c)` with `c = a - b`.
Change-Id: I4a0bf83013065176782b18d0eb40d96c11a54791
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Subtract (a, b, c)` with `c = a - b`.
Change-Id: If35c90d0e7d523f67f94d542e37fdca43bb16d7c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `LAnd (a, b)` with `a && b`.
Change-Id: I7d74e6a2ce4ee98c1c0f5b412e20661c5196735e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `LAnd (a, b)` with `a && b`.
Change-Id: I72604a0efa2d8fcdf39cf5a8b70082aeb32dddab
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60464
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `LAnd (a, b)` with `a && b`.
Change-Id: I8c3323e1d367872e9f2a134eaf4ebd9e35f74313
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `LAnd (a, b)` with `a && b`.
Change-Id: Ic578506dd2a1ab4341361f1a3b435372f2dac260
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace Index(FOO, 1337) with FOO[1337].
Change-Id: I628a6108e12ba784542474ebe58285754f40169c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace Index(FOO, 1337) with FOO[1337].
Change-Id: Ie499f27acd13569095749e095d7898890da6985d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace Index(FOO, 1337) with FOO[1337].
Change-Id: I2fb96e338b332f4fbb3bd23fb07bb1ca36c19c49
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60457
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace Index(FOO, 1337) with FOO[1337].
Change-Id: I0b1fe0fcdf2862dc76f07ef1478929f7c726ac47
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60455
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4b829a54bbbb8e7442e59feaf2e7dbf8556b590d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ic26c24d1246f8a40191e02229e66f6a893e488fa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Built with BUILD_TIMELESS=1 and coreboot.rom remains identical.
Change-Id: Id343bde61706d4d1de2102c3567141e427d8126d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Built with BUILD_TIMELESS=1 and coreboot.rom remains identical.
Change-Id: I2b06f74be155e0c4053a38a1c5fd30ff6715111e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Built with BUILD_TIMELESS=1 and coreboot.rom remains identical.
Change-Id: Ib59cba7bf553e8323c20fd9aa3474f3ecccf465a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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According to util/kbc1126/README.md, for these ECs to work, the
address and size of their two firmware should be written to $s-0x100`
(`$s` means the image size, done with kbc1126_ec_insert), which means
that every existing section (especially those used to store code)
should not overlap this address, otherwise the bootblock will get
damaged when inserting firmwares of the EC.
In this commit, ecfw_ptr is a structure initialized at build time
according to CONFIG_KBC1126_FW1_OFFSET and CONFIG_KBC1126_FW2_OFFSET
(to do so, they should be redefined as hex), and linked to
CONFIG_ECFW_PTR_ADDR within bootblock, so kbc1126_ec_insert is not
needed at build time any more.
Test passed on Elitebook Folio 9470m.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Some boards with the chrome EC will need to support more than 4
temperature sensors, so modify the number of TSRs supported when
generating the ACPI code. Note that the EC memory map already has
support for up to 16 TSRs, so no change is required on the EC
side.
BUG=b:207585491
TEST=with previous patch and some test data in brya0 overridetree.cb,
dump the SSDT and verify that all of the existing Methods for TSR0-TSR3
are also added for TSR4, as well as all Notify, etc.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Id002230bc872b0f818b0bf2b87987298189c973d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59633
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new config for boards with dGPUs to enable reporting fan duty and
temperature. The dGPU is not yet enabled on any boards, so it always
reports the temp as 0. However, the EC firmware does use the dGPU's fan
and so reports valid information for fan speed.
Change-Id: Iae1063ee6a082a77ed026178eb9471bbc2b2fadf
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Given EC CON and associated USB port objects, custom_pld or pld_group
information is retrieved from port and added to ACPI table as _PLD field
for typec connector.
BUG=b:202446737
TEST=emerge-brya coreboot & SSDT dump in Brya test device
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ibc56ecd4e8954ffaace3acd9528a064b5fa2cf6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add EC support that supports different Q Events and EC memory.
Created from the ITE IT5570E and IT8987E datasheets, all using
data port 0x4e.
Tested with Ubuntu 20.04.3 and Windows 10 on:
* StarBook Mk V (TGL + IT5570E):
* ITE Firmware 1.00
* Merlin Firmware 1.00
* LabTop Mk IV (CML + IT8987E):
* ITE Firmware 1.04
* LabTop Mk III (KBL + IT8987E):
* ITE Firmware 3.12
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58343
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove old code in favour of new format of firmware API.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iaf8f37a08c232b8754e57f022782f21284fa07dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Register USB-C mux operations to the generic interface.
BUG=b:192947843
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: I576c9e4c6c82d6b4055b0a0a9a75c677d4b05220
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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google_chromeec_usb_pd_get_info() is used in ec.c only. Make it
static and drop from ec.h.
BUG=b:192947843
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: I4b3df4223d5c26ea1c1a52b26f7d49fa4c947de8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add google_chromeec_get_usbc_mux_info() to obtain USB-C mux
related information.
BUG=b:192947843
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Idc27f23214c2d5b91334ae3efe248100329964ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add API to allow AP to send the command to EC to enter DP ALT mode
and API to wait for DP HPD event.
BUG=b:192947843
TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name. Build
coreboot and update your system. Boot the system you will find below
message in the coreboot log with or without USB-C display connected:
'HPD ready after %lu ms' or 'HPD not ready after %ldms. Abort.'.
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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1. Update google_chromeec_pd_get_amode() to return bitmask.
2. Update google_chromeec_wait_for_displayport() to handle the
updated return value of google_chromeec_pd_get_amode().
3. Drop google_chromeec_pd_get_amode() from ec.h and make it static
because it's not used outside of ec.c.
BUG=b:192947843
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: I6020c4305e30018d4c97d862c16e8d642c951765
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add parameter `active_cable` to obtain the cable type
(active or passive) which is needed for USB-C configuration for
some SoCs (at least Intel TGL and ADL), change the function name to
google_chromeec_usb_pd_get_info() for better understanding.
BUG=b:192947843
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Ie91a3096d49d5dde75e60ab0f2f38152cef720f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This code is identical except for some renaming.
Change-Id: I93795a6087ce0daca27c0d5038a1febd6ca9c775
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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This change copies ec_commands.h directly from Chromium OS EC repo at
sha 8c2c6bd5b1d44b367929af498d4d4b0df126a4ef.
BUG=b:188073399
TEST=Build coreboot
BRANCH=None
Change-Id: I674cb860adb6b8497a8aecf47952ed8f85ddaa70
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Implement _BIX method to expose battery cycle count.
Requires an EC version with support for cycle count.
Change-Id: I5f7a1d275caff59960aaf9c39b9c707970350987
Signed-off-by: Ian Douglas Scott <idscott@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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There was no code attached to this driver and hence one couldn't hook
it up to any device. Even if mentioned in the `devicetree.cb` it was
still dead code.
Change-Id: I12415ea9e0120b1d00524f8f39f9b2d02f46ba05
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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- Chromebook have some platform need support MICMUTE and KBDILLUMTOGGLE.
- Sync ec_commands.h
This change syncs the coreboot version of google ec_commands.h with the
ec_commands.h from the google ec repository. This is a straight copy
except for the the copyright header.
BUG=b:194146863
BRANCH=none
TEST=check on evtest
type 4 (EV_MSC), code 4 (MSC_SCAN), value 9e
type 1 (EV_KEY), code 228 (KEY_KBDILLUMTOGGLE), 1
type 4 (EV_MSC), code 4 (MSC_SCAN), value 9b
type 1 (EV_KEY), code 248 (KEY_MICMUTE), value 1
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: Ie4fa3e627f448265f72279704d258b2d3fe8fc17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56710
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Simplify some operations to get rid of unnecessary assignments.
Change-Id: I02c93d42ce1de693d5d58fd9a29ccd5bff0f5978
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the
same.
Change-Id: I9f08b048d41ab7a5d7d7dc735779ea019517491a
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56608
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Use mathematical operators instead of their equivalent methods.
Change-Id: I5b1d5d9882eae5e8bcf2d97bcefaeea1a7ad8f4d
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56607
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Use bit-wise and logical operators instead of their equivalent methods.
Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the
same.
Change-Id: I30807e14b2a9a8203a76d418f586423bcaec2a3a
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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Replace `Store()` with the assignment operator.
Change-Id: I2931a3e1b9a55198ec4dacc9218b6c9028052631
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Use `FOOO[1337]` instead of `Index(FOOO, 1337)`.
Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the
same.
Change-Id: I4f5d5cb8ce8c3ae37dc44ca87bd67596af9feee8
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I7d4fb69a223e3b48a790e9144d2682619c18d513
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Replace `Store("...", Debug)` with `Printf("...")`.
Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the
same.
Change-Id: Ie1a1f7320ef2850e4f861b1426240e6940036844
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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The GPE offset of 16 is PCH specific.
Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the
same.
Change-Id: I4ec38fc28d2436f84a090bb4ab38f20612cfd795
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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The patch adds an interface for configuring GPIOs inside the Kontron
CPLD/EC. This allows to statically define the mode for each GPIO pin
in devicetree.cb of the motherboard or carrier board. For example:
chip ec/kontron/kempld
device gpio 0 on
register "gpio[0]" = "KEMPLD_GPIO_INPUT"
register "gpio[4]" = "KEMPLD_GPIO_OUTPUT_LOW"
register "gpio[5]" = "KEMPLD_GPIO_OUTPUT_HIGH"
register "gpio[11]" = "KEMPLD_GPIO_DEFAULT"
end
end
In this case, <device gpio 0>, like all other devices, is not a real
device inside the EC. These definitions are used to understand the EC
resources and systematize configuration options, but if mark this as
<off>, the initialization step will be skipped in the driver code.
Use KEMPLD_GPIO_DEFAULT or skip it in devicetree.cb to not configure
the GPIO and keep the default mode after CPLD reset.
This work is based on code from the drivers/gpio/gpio-kempld.c linux
driver. Tested on Kontron mAL-10 COMe module [1].
[1] CB:54380 , Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e
Change-Id: Id767aa451fbf2ca1c0dccfc9aa2c024c6f37c1bb
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47595
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
google_chromeec_get_event returns 0 for no event. Return
EC_HOST_EVENT_NONE=0 to improve readability.
BUG=b:184074997
TEST=Build and boot guybrush without error
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ic08ed9ccdd7c0023d0fe8b641fcf60dca495a242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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This change syncs the coreboot version of google ec_commands.h with the
ec_commands.h from the google ec repository. This is a straight copy
except for the the copyright header.
BUG=b:184074997
TEST=Build and boot guybrush
BRANCH=None
Change-Id: I095c3316d720328cb7b8dd1b72ffc108208b14bd
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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SYSTEM_TYPE_CONVERTIBLE is not valid SMBIOS enclosure type,
but selecting it implies SMBIOS_ENCLOSURE_CONVERTIBLE.
Change-Id: Ib658af7b80586428b22f08a738964637e1fbd17a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Somehow, enabling the notification to the OS driver breaks the
functionality it was meant to enable. Until this can be resolved,
disable the driver notification, so that the key functions as intended.
Test: build/boot librem_bdw and librem_skl boards, verify trackpad
enable toggle via Fn+F1 works properly.
Change-Id: Ic7bdb3154a87c4202b5ee1fd333281ef78db1104
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55657
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
google_chromeec_get_event returns an event number and 0 when there's no event.
This function is usually called in a loop until there are no more events, so
it makes sense to return 0 (i.e. no event) when there's an error.
BUG=b:184074997
TEST=Boot guybrush, no ec errors
Change-Id: I6c0186e4637af9ae24f45cce3638f0913227d6a7
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
All functions in ec_skuid.c except google_chromeec_get_board_sku()
are for SMBIOS platforms. Move these functions to a new file to allow
non-SMBIOS platforms to use google_chromeec_get_board_sku() without
having to declare MAINBOARD_SMBIOS_MANUFACTURER.
BUG=none
TEST=emerge-cherry coreboot
BRANCH=none
Change-Id: I8916223f5f04afe4761be4ad3313e900efae90d4
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Support for Star Labs labtop series EC
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add parentheses around macro parameters to avoid operation order issues.
Change-Id: I2d4552abaeda5702619cc53e9dfae1f17b048e67
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: Ia278b538a8904651d16c37d095972fa78e264288
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/7S5OJMLQUEIU6YK36JTTRINF5OOCI66V/
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Building google/sarien with a 64-bit compiler (x86_64-linux-gnu) fails
with the error below.
src/ec/google/wilco/mailbox.c: In function 'wilco_ec_transfer':
src/ec/google/wilco/mailbox.c:184:43: error: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
184 | printk(BIOS_ERR, "%s: data too short (%lu bytes, expected %zu)",
| ~~^
| |
| long unsigned int
| %u
185 | __func__, rs.data_size - skip_size, msg->response_size);
| ~~~~~~~~~~~~~~~~~~~~~~~~
| |
| size_t {aka unsigned int}
`data_size` has type `uint16_t`, and `skip_size` has type `size_t`,
whose size differs in 32-bit (unsigned int) and 64-bit (unsigned long).
So use the length modifier `z` for a `size_t` argument.
Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110
Change-Id: Ida27323daeed9b8ff487302d0f3d6fcce0bbb705
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie
|
|
This adds the required method to access temperature data from the
ChromeEC.
BUG=b:186166365
TEST=Boot guybrush to the OS and verify temperatures
$ tail /sys/devices/virtual/thermal/thermal_zone*/temp
==> /sys/devices/virtual/thermal/thermal_zone0/temp <==
31900
==> /sys/devices/virtual/thermal/thermal_zone1/temp <==
34900
==> /sys/devices/virtual/thermal/thermal_zone2/temp <==
31900
==> /sys/devices/virtual/thermal/thermal_zone3/temp <==
33900
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I418b6691a7d00a4c2d89c9c1fe8f9416602be0f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54133
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
coreboot needs to access EC RFWU entry in order to suspend and resume PD
and modes setting. This change adds ec_retimer_fw_update implementation
for retimer firmware upgrade.
BUG=b:186521258
TEST=Build image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ib937d8bd72fc39487854773573b435bf2add672a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52713
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Along with upstream kernel for Retimer firmware update, coreboot changes
the ec_retimer_fw_update format. This change removes this API and will
add implementation later once the dependent definition is complete.
BUG=b:186521258
TEST=Build image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I2d074b84fb3cb87b443871104b72b6c316af5279
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.
Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
This change is needed to update the option API to use unsigned integers.
The CMOS option system does not support negative numbers.
The volume field is only 8 bits long. Do not set the volume if it is out
of range. Also, use an out-of-range value as fallback to skip setting
the volume when it cannot be read using the option API, to preserve the
current behavior.
Change-Id: I7af68bb5c1ecd4489ab4b826b9a5e7999c77b1ff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Rewrite google_chromeec_status_check to use stopwatch instead of a
delay in a while loop. In practice the while loop ends up taking
much longer than one second to timeout. Using stopwatch library will
accurately timeout after one second.
BUG=b:183524609
TEST=Build and run on guybrush
BRANCH=None
Change-Id: I363ff7453bcf81581884f92797629a6f96d42580
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
- remove unused Kconfig options
- change ACPI device name and HID
- remove ACPI for unused color keyboard backlight
- add support for RGB notification LED
- rename Wifi LED ACPI variable
- set some battery info defaults not populated by the EC
Change-Id: I72eca9deb83e5a6d919d6fcbd3b354fbf6e7a925
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Initial commit is a clone of ec/system76/ec with string changes;
Purism-specific functionality will be added in subsequent commits.
Change-Id: I8c51724e6dbfe1bc09496537f9e031643f95c755
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: Ibca7660ed03525903a1146a1fb2937550406bee8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Change-Id: Ie5cb54b171244be71848a59a788ed8d42b3e3161
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and SSFC is
not set, all fw_config is invalidated. But for some platform this may
not be necessary, we can treat missing SSFC as zero and use other 32
bits of firmware config.
BUG=b:184809649
TEST=boot and check fw_config is not -1 even if ssfc is not set
BRANCH=zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I21c7b0d449a694d28ad7b3f14b035e3a5830030a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
The conversion to ASL 2.0 syntax in commit 81d55cf introduced a
regression triggering a BUG in Linux when reading the battery current.
Correct the wrongly-converted calculation.
Fixes: 81d55cf ("src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0")
Tested-by: Andrew A. I. <aidron@yandex.ru>
Change-Id: I1cea8f56eb0a674005582c87cad89f10a02d0701
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52144
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I667accd980da6384a7cc6a3f4eb7565b8b3b2400
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I3a67008d84da614e8c8cbfa681a0fdd19ff1d77f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexey Vazhnov <vazhnov@boot-keys.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Fetch second source factory cache configuration (SSFC) as an optional
element to the firmware config interface. Introduce a Kconfig so that it
can be enabled and used on required mainboards.
BUG=b:177055126
TEST=Build and Boot to OS in Magolor.
Change-Id: I81137406d21e77b5d58a33f66778e13cf16c85c7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51094
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When the EC is reset on PLTRST this information will be lost, causing
system control interrupts to potentially stop functioning.
Change-Id: I137ef6c574a372601bc51f6e815158767acd0e1b
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50489
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I7cc47536b0c1e2c903df29402090abfccde82406
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I5de6c7da2440d682378a4ceb89b4bedd689dad60
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I078ca86cf9e948d4dd4338fca842ae3e580228ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
- Move ACPI code for Apple MacBooks to a separate directory to avoid
its duplication in mainboards
- Add AC and lid implementations for newer generations
- Rewrite old code using the new ASL syntax
Tested on MBA 5,2, MBP 8,1 and MBP 10,1.
Change-Id: I3d4585aac8e3ebbfed6ce4d4e39fbc33ac983069
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This fixes the fan always running at full speed on ProBook 6360b,
EliteBook 8470p and ProBook 640 G1 (because the fan control command was
not sent).
On the ProBook 6360b, the EC needs about 30 ms to process the first
command on a cold boot, but other models such as the ProBook 640 G1 need
more time.
Change-Id: I8623af75c062d6aa69d4412e0627d426c69019fb
Signed-off-by: Pablo Stebler <pablo@stebler.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ie5c88f8acee16ff77f9707d7ed56436bf0d521b1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I934f9d1664f657597f15daed2d2d0c41cd124d21
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Ifd85d2eabbda4e25406f20391489c0e7ad314348
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I4823b84d851d7d1f0f48be44ab28e7365b553b6f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Ic773f8404c24fc886e8420a5f4b3e00b2d752ba2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Kernel needs to access EC RFWU entry in order to retrieve from EC about
port and mux info and set EC operations like modes change. This change
provides EC RFWU path and update for Retimer driver usage.
BUG=b:162528867
TEST=Booted to kernel and verified EC RFWU path from ACPI SSDT table.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I3817d93cfdeedf15825dab6c537b151fd063338b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49257
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The RFWU byte is defined as Bits[3:0] for port number and Bits[7:4] for
operations. The supported operations are:
RETIMER_FW_UPDATE_PORT_INFO 0
RETIMER_FW_UPDATE_PD_SUSPEND 1
RETIMER_FW_UPDATE_PD_RESUME 2
RETIMER_FW_UPDATE_GET_MUX 3
RETIMER_FW_UPDATE_SET_USB 4
RETIMER_FW_UPDATE_SET_SAFE 5
RETIMER_FW_UPDATE_SET_TBT 6
RETIMER_FW_UPDATE_DISCONNECT 7
BUG=b:162528867
TEST=Booted to kernel and verified RFWU entry from ACPI DSDT ERAM field.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1ba04c6357b6fd0cc33ffce33e7e430539bace79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49051
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I87d5a5fa584b4250bc8b532c046e6bd070e33e81
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
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Change-Id: I7f567f2b4c582e4b2bb102ef0e0f68c5bf6cfb9e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
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Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: Iee19e7518ffaacd9a847cb6d28c839d4ec464514
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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They all operate on that file, so just add it globally.
Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Now that intermediate coreboot.pre manipulation is serialized within
the build system, remove the flock calls.
Change-Id: I8a767918aec5fcb7127ebb19ac46e58bed7967fb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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